Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_to_prog_fifo.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.67	100.00	64.35			85.71	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	90.30	100.00	80.00			90.91

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417237448	36383836	0	0
DepthKnown_A	417237448	416310977	0	0
RvalidKnown_A	417237448	416310977	0	0
WreadyKnown_A	417237448	416310977	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	36383836	0	0
T1	33118	3061	0	0
T2	3589	111	0	0
T3	1199	20	0	0
T4	141440	155423	0	0
T5	241161	119892	0	0
T6	2308	124	0	0
T7	48074	28779	0	0
T12	3534	507	0	0
T20	2338	537	0	0
T21	1341	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417237448	45824012	0	0
DepthKnown_A	417237448	416310977	0	0
RvalidKnown_A	417237448	416310977	0	0
WreadyKnown_A	417237448	416310977	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	45824012	0	0
T1	33118	9489	0	0
T2	3589	468	0	0
T3	1199	20	0	0
T4	141440	481695	0	0
T5	241161	119892	0	0
T6	2308	545	0	0
T7	48074	20817	0	0
T12	3534	507	0	0
T20	2338	537	0	0
T21	1341	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417237448	2356652	0	0
DepthKnown_A	417237448	416310977	0	0
RvalidKnown_A	417237448	416310977	0	0
WreadyKnown_A	417237448	416310977	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	2356652	0	0
T4	141440	10125	0	0
T5	241161	1128	0	0
T6	2308	10	0	0
T7	48074	0	0	0
T12	3534	0	0	0
T13	843	0	0	0
T16	3600	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	24	0	0
T27	0	20864	0	0
T33	0	10617	0	0
T34	0	8589	0	0
T40	0	439	0	0
T41	0	2510	0	0
T42	0	8329	0	0
T56	983	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417237448	3573028	0	0
DepthKnown_A	417237448	416310977	0	0
RvalidKnown_A	417237448	416310977	0	0
WreadyKnown_A	417237448	416310977	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	3573028	0	0
T4	141440	31170	0	0
T5	241161	1128	0	0
T6	2308	41	0	0
T7	48074	0	0	0
T12	3534	0	0	0
T13	843	0	0	0
T16	3600	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	24	0	0
T27	0	20864	0	0
T33	0	33060	0	0
T34	0	27750	0	0
T40	0	43	0	0
T41	0	266	0	0
T42	0	8329	0	0
T56	983	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417237448	4082651	0	0
DepthKnown_A	417237448	416310977	0	0
RvalidKnown_A	417237448	416310977	0	0
WreadyKnown_A	417237448	416310977	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	4082651	0	0
T1	33118	499	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	9074	0	0
T5	241161	972	0	0
T6	2308	20	0	0
T7	48074	10994	0	0
T8	0	10528	0	0
T12	3534	0	0	0
T20	2338	146	0	0
T21	1341	0	0	0
T28	0	14800	0	0
T40	0	84	0	0
T42	0	12295	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417237448	4891452	0	0
DepthKnown_A	417237448	416310977	0	0
RvalidKnown_A	417237448	416310977	0	0
WreadyKnown_A	417237448	416310977	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	4891452	0	0
T1	33118	1591	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	28647	0	0
T5	241161	972	0	0
T6	2308	97	0	0
T7	48074	5894	0	0
T8	0	10528	0	0
T12	3534	0	0	0
T20	2338	146	0	0
T21	1341	0	0	0
T28	0	14800	0	0
T40	0	42	0	0
T42	0	5043	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417237448	29876439	0	0
DepthKnown_A	417237448	416310977	0	0
RvalidKnown_A	417237448	416310977	0	0
WreadyKnown_A	417237448	416310977	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	29876439	0	0
T1	33118	2562	0	0
T2	3589	111	0	0
T3	1199	20	0	0
T4	141440	136224	0	0
T5	241161	117792	0	0
T6	2308	94	0	0
T7	48074	16869	0	0
T12	3534	507	0	0
T20	2338	391	0	0
T21	1341	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	417237448	37359532	0	0
DepthKnown_A	417237448	416310977	0	0
RvalidKnown_A	417237448	416310977	0	0
WreadyKnown_A	417237448	416310977	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	37359532	0	0
T1	33118	7898	0	0
T2	3589	468	0	0
T3	1199	20	0	0
T4	141440	421878	0	0
T5	241161	117792	0	0
T6	2308	407	0	0
T7	48074	14923	0	0
T12	3534	507	0	0
T20	2338	391	0	0
T21	1341	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417237448	416310977	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T22
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414715506	3554016	0	0
DepthKnown_A	414715506	413874116	0	0
RvalidKnown_A	414715506	413874116	0	0
WreadyKnown_A	414715506	413874116	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	414715506	3554016	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	3554016	0	0
T4	141440	31170	0	0
T5	241161	1128	0	0
T6	2308	41	0	0
T7	48074	0	0	0
T12	3534	0	0	0
T13	843	0	0	0
T16	3600	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	24	0	0
T27	0	20864	0	0
T33	0	33060	0	0
T34	0	27750	0	0
T40	0	43	0	0
T41	0	266	0	0
T42	0	8329	0	0
T56	983	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	3554016	0	0
T4	141440	31170	0	0
T5	241161	1128	0	0
T6	2308	41	0	0
T7	48074	0	0	0
T12	3534	0	0	0
T13	843	0	0	0
T16	3600	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	24	0	0
T27	0	20864	0	0
T33	0	33060	0	0
T34	0	27750	0	0
T40	0	43	0	0
T41	0	266	0	0
T42	0	8329	0	0
T56	983	0	0	0