Unified Coverage Report :: Module Instance :: tb.dut.u_tl_adapter_eflash.u_rspfifo

Module Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.18	100.00	84.17			96.55	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_bank_sequence_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.09	100.00	92.86		87.50	100.00		gen_prim_flash_banks[0].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.35	100.00	91.67		93.75	100.00		gen_prim_flash_banks[1].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.45	100.00	87.23	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	97.83	100.00	91.30	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.44	100.00	87.18	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.63	100.00	90.53			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.44	100.00	87.18	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.63	100.00	90.53			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	80.56			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.63	100.00	90.53			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.60	100.00	82.98	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	97.83	100.00	91.30	100.00		100.00

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T13

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T13

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T24,T25
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T13

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T13

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T13

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T59,T48
1	0	Covered	T1,T7,T13
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T7,T13
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414715506	5177345	0	0
DepthKnown_A	414715506	413874116	0	0
RvalidKnown_A	414715506	413874116	0	0
WreadyKnown_A	414715506	413874116	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	414715506	5177345	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	5177345	0	0
T1	33118	1229	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	0	0	0
T5	241161	0	0	0
T6	2308	0	0	0
T7	48074	16304	0	0
T8	0	17000	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	320	0	0
T24	0	16521	0	0
T28	0	16223	0	0
T40	0	140	0	0
T42	0	41330	0	0
T53	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	5177345	0	0
T1	33118	1229	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	0	0	0
T5	241161	0	0	0
T6	2308	0	0	0
T7	48074	16304	0	0
T8	0	17000	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	320	0	0
T24	0	16521	0	0
T28	0	16223	0	0
T40	0	140	0	0
T42	0	41330	0	0
T53	0	10	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T13

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T13

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T7,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T13

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T7,T13
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414715506	34834415	0	0
DepthKnown_A	414715506	413874116	0	0
RvalidKnown_A	414715506	413874116	0	0
WreadyKnown_A	414715506	413874116	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	414715506	34834415	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	34834415	0	0
T1	33118	337	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	0	0	0
T5	241161	0	0	0
T6	2308	0	0	0
T7	48074	32086	0	0
T8	0	615883	0	0
T12	3534	0	0	0
T13	0	34	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	882	0	0
T24	0	33262	0	0
T28	0	43400	0	0
T40	0	479	0	0
T42	0	149062	0	0
T53	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	34834415	0	0
T1	33118	337	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	0	0	0
T5	241161	0	0	0
T6	2308	0	0	0
T7	48074	32086	0	0
T8	0	615883	0	0
T12	3534	0	0	0
T13	0	34	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	882	0	0
T24	0	33262	0	0
T28	0	43400	0	0
T40	0	479	0	0
T42	0	149062	0	0
T53	0	17	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414715506	113467509	0	0
DepthKnown_A	414715506	413874116	0	0
RvalidKnown_A	414715506	413874116	0	0
WreadyKnown_A	414715506	413874116	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	414715506	113467509	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	113467509	0	0
T1	33118	223	0	0
T2	3589	152	0	0
T3	1199	32	0	0
T4	141440	481719	0	0
T5	241161	82991	0	0
T6	2308	570	0	0
T7	48074	9743	0	0
T12	3534	212	0	0
T20	2338	105	0	0
T21	1341	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	113467509	0	0
T1	33118	223	0	0
T2	3589	152	0	0
T3	1199	32	0	0
T4	141440	481719	0	0
T5	241161	82991	0	0
T6	2308	570	0	0
T7	48074	9743	0	0
T12	3534	212	0	0
T20	2338	105	0	0
T21	1341	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T42
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T42
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414715506	89116480	0	0
DepthKnown_A	414715506	413874116	0	0
RvalidKnown_A	414715506	413874116	0	0
WreadyKnown_A	414715506	413874116	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	414715506	89116480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	89116480	0	0
T1	33118	195	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	545623	0	0
T5	241161	148645	0	0
T6	2308	0	0	0
T7	48074	9076	0	0
T8	0	12266	0	0
T12	3534	0	0	0
T13	0	7	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	177120	0	0
T28	0	10499	0	0
T40	0	66443	0	0
T42	0	137191	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	89116480	0	0
T1	33118	195	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	545623	0	0
T5	241161	148645	0	0
T6	2308	0	0	0
T7	48074	9076	0	0
T8	0	12266	0	0
T12	3534	0	0	0
T13	0	7	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	177120	0	0
T28	0	10499	0	0
T40	0	66443	0	0
T42	0	137191	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T42,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T53,T60,T61
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T28,T42,T22
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T53,T60,T61
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T28,T42,T22
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414404948	3030641	0	0
DepthKnown_A	414404948	413563558	0	0
RvalidKnown_A	414404948	413563558	0	0
WreadyKnown_A	414404948	413563558	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	414404948	3030641	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	3030641	0	0
T1	33118	108	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	0	0	0
T5	241161	0	0	0
T6	2308	0	0	0
T7	48074	8299	0	0
T8	0	7907	0	0
T12	3534	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	192	0	0
T24	0	8712	0	0
T28	0	9012	0	0
T40	0	74	0	0
T42	0	44856	0	0
T53	0	119	0	0
T55	0	7255	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	3030641	0	0
T1	33118	108	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	0	0	0
T5	241161	0	0	0
T6	2308	0	0	0
T7	48074	8299	0	0
T8	0	7907	0	0
T12	3534	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	192	0	0
T24	0	8712	0	0
T28	0	9012	0	0
T40	0	74	0	0
T42	0	44856	0	0
T53	0	119	0	0
T55	0	7255	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414404948	54278676	0	0
DepthKnown_A	414404948	413563558	0	0
RvalidKnown_A	414404948	413563558	0	0
WreadyKnown_A	414404948	413563558	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	414404948	54278676	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	54278676	0	0
T1	33118	679	0	0
T2	3589	565	0	0
T3	1199	128	0	0
T4	141440	2586	0	0
T5	241161	774	0	0
T6	2308	158	0	0
T7	48074	25225	0	0
T12	3534	768	0	0
T20	2338	493	0	0
T21	1341	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	54278676	0	0
T1	33118	679	0	0
T2	3589	565	0	0
T3	1199	128	0	0
T4	141440	2586	0	0
T5	241161	774	0	0
T6	2308	158	0	0
T7	48074	25225	0	0
T12	3534	768	0	0
T20	2338	493	0	0
T21	1341	128	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T54
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414404948	14233877	0	0
DepthKnown_A	414404948	413563558	0	0
RvalidKnown_A	414404948	413563558	0	0
WreadyKnown_A	414404948	413563558	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	414404948	14233877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	14233877	0	0
T1	33118	255	0	0
T2	3589	281	0	0
T3	1199	64	0	0
T4	141440	887	0	0
T5	241161	289	0	0
T6	2308	74	0	0
T7	48074	13160	0	0
T12	3534	384	0	0
T20	2338	210	0	0
T21	1341	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	14233877	0	0
T1	33118	255	0	0
T2	3589	281	0	0
T3	1199	64	0	0
T4	141440	887	0	0
T5	241161	289	0	0
T6	2308	74	0	0
T7	48074	13160	0	0
T12	3534	384	0	0
T20	2338	210	0	0
T21	1341	64	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414715506	12918979	0	0
DepthKnown_A	414715506	413874116	0	0
RvalidKnown_A	414715506	413874116	0	0
WreadyKnown_A	414715506	413874116	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	414715506	12918979	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	12918979	0	0
T1	33118	64	0	0
T2	3589	281	0	0
T3	1199	64	0	0
T4	141440	64	0	0
T5	241161	64	0	0
T6	2308	64	0	0
T7	48074	6834	0	0
T12	3534	384	0	0
T20	2338	210	0	0
T21	1341	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	12918979	0	0
T1	33118	64	0	0
T2	3589	281	0	0
T3	1199	64	0	0
T4	141440	64	0	0
T5	241161	64	0	0
T6	2308	64	0	0
T7	48074	6834	0	0
T12	3534	384	0	0
T20	2338	210	0	0
T21	1341	64	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T42,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T13

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T13

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T7,T42,T22
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T13

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T13

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T13

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T42,T22
1	0	Covered	T1,T7,T13
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T7,T13
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414404948	3061263	0	0
DepthKnown_A	414404948	413563558	0	0
RvalidKnown_A	414404948	413563558	0	0
WreadyKnown_A	414404948	413563558	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	414404948	3061263	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	3061263	0	0
T1	33118	112	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	0	0	0
T5	241161	0	0	0
T6	2308	0	0	0
T7	48074	9942	0	0
T8	0	9093	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	215	0	0
T24	0	9400	0	0
T28	0	8226	0	0
T40	0	66	0	0
T42	0	35657	0	0
T53	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	413563558	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	414404948	3061263	0	0
T1	33118	112	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	0	0	0
T5	241161	0	0	0
T6	2308	0	0	0
T7	48074	9942	0	0
T8	0	9093	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	215	0	0
T24	0	9400	0	0
T28	0	8226	0	0
T40	0	66	0	0
T42	0	35657	0	0
T53	0	6	0	0