Group : tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg
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Group : tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
0.00 0.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sec_cm_0/prim_onehot_check_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if 0.00 1 100 1 64 64




Group Instance : tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 2 0 0.00


Variables for Group Instance tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_onehot_enable_fault 1 1 0 0.00 100 1 1 0
cp_onehot_fault 1 1 0 0.00 100 1 1 0


Summary for Variable cp_onehot_enable_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_onehot_enable_fault

Uncovered bins
NAMECOUNTAT LEASTNUMBER
hit 0 1 1



Summary for Variable cp_onehot_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_onehot_fault

Uncovered bins
NAMECOUNTAT LEASTNUMBER
hit 0 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%