Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22397113	1		T1	64		T2	10373		T3	158203
full_word	7310585	1		T1	43		T2	1297		T3	33288

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29707358	1		T1	107		T2	11670		T3	191491
auto[TlIntgErrCmd]	120	1		T58	9		T231	4		T207	7
auto[TlIntgErrData]	99	1		T58	3		T231	2		T207	6
auto[TlIntgErrBoth]	121	1		T58	8		T231	4		T207	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	25747128	1		T1	60		T2	10539		T3	168632
auto[1]	3960570	1		T1	47		T2	1131		T3	22859

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21774978	1		T1	59		T2	10247		T3	155526
auto[TlIntgErrNone]	partial	auto[1]	621815	1		T1	5		T2	126		T3	2677
auto[TlIntgErrNone]	full_word	auto[0]	3972000	1		T1	1		T2	292		T3	13106
auto[TlIntgErrNone]	full_word	auto[1]	3338565	1		T1	42		T2	1005		T3	20182
auto[TlIntgErrCmd]	partial	auto[0]	48	1		T58	4		T231	2		T207	3
auto[TlIntgErrCmd]	partial	auto[1]	66	1		T58	5		T231	2		T207	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T312	1		T351	1		T352	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T346	1		T349	1		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1		T58	1		T231	2		T207	3
auto[TlIntgErrData]	partial	auto[1]	51	1		T58	2		T207	2		T208	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T207	1		T210	1		T309	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T353	1		T347	1		T354	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1		T58	4		T231	3		T207	3
auto[TlIntgErrBoth]	partial	auto[1]	66	1		T58	4		T231	1		T207	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T277	1		T355	1		T346	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T351	1		T356	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18042	1		T56	110		T57	567		T58	14
full_word	3446572	1		T2	40		T3	40798		T23	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3464302	1		T2	40		T3	40798		T23	10
auto[TlIntgErrCmd]	98	1		T58	5		T231	3		T207	9
auto[TlIntgErrData]	112	1		T58	9		T231	2		T207	3
auto[TlIntgErrBoth]	102	1		T58	4		T231	5		T207	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3441240	1		T2	40		T3	40798		T23	10
auto[1]	23374	1		T56	110		T57	868		T58	10

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1050	1		T56	12		T57	28		T194	7
auto[TlIntgErrNone]	partial	auto[1]	16711	1		T56	98		T57	539		T194	578
auto[TlIntgErrNone]	full_word	auto[0]	3440065	1		T2	40		T3	40798		T23	10
auto[TlIntgErrNone]	full_word	auto[1]	6476	1		T56	12		T57	329		T194	268
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T58	1		T207	2		T208	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1		T58	3		T231	1		T207	7
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T309	1		T348	1		T357	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T58	1		T231	2		T277	1
auto[TlIntgErrData]	partial	auto[0]	55	1		T58	3		T231	1		T208	8
auto[TlIntgErrData]	partial	auto[1]	43	1		T58	4		T207	3		T208	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T58	2		T231	1		T351	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T277	1		T350	2		T312	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T58	2		T231	2		T207	3
auto[TlIntgErrBoth]	partial	auto[1]	62	1		T58	1		T231	3		T207	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T353	1		T349	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T58	1		T350	1		T309	1