Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T23

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1443873148	1441197612	0	0
CheckNGreaterZero_A	3544	3544	0	0
GntImpliesReady_A	1443873148	349292419	0	0
GntImpliesValid_A	1443873148	349292419	0	0
GrantKnown_A	1443873148	1441197612	0	0
IdxKnown_A	1443873148	1441197612	0	0
IndexIsCorrect_A	1443873148	349292419	0	0
NoReadyValidNoGrant_A	1443873148	172807980	0	0
Priority_A	1443873148	371869711	0	0
ReadyAndValidImplyGrant_A	1443873148	349292419	0	0
ReqAndReadyImplyGrant_A	1443873148	349292419	0	0
ReqImpliesValid_A	1443873148	371869711	0	0
ValidKnown_A	1443873148	1441197612	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	1441197612	0	0
T1	5844	4760	0	0
T2	386408	382100	0	0
T3	1574256	1573924	0	0
T4	335112	315648	0	0
T5	1744384	1744032	0	0
T9	1604820	1604760	0	0
T22	141480	141140	0	0
T23	5148	4840	0	0
T24	4504	3680	0	0
T25	5740	5468	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3544	3544	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T9	4	4	0	0
T22	4	4	0	0
T23	4	4	0	0
T24	4	4	0	0
T25	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	349292419	0	0
T1	2922	132	0	0
T2	386408	142382	0	0
T3	1574256	497718	0	0
T4	335112	103152	0	0
T5	1744384	854600	0	0
T9	1604820	514658	0	0
T10	106146	18486	0	0
T15	0	239052	0	0
T16	0	844	0	0
T21	0	255794	0	0
T22	141480	1088	0	0
T23	5148	84	0	0
T24	4504	132	0	0
T25	5740	64	0	0
T61	0	18694	0	0
T77	0	600	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	349292419	0	0
T1	2922	132	0	0
T2	386408	142382	0	0
T3	1574256	497718	0	0
T4	335112	103152	0	0
T5	1744384	854600	0	0
T9	1604820	514658	0	0
T10	106146	18486	0	0
T15	0	239052	0	0
T16	0	844	0	0
T21	0	255794	0	0
T22	141480	1088	0	0
T23	5148	84	0	0
T24	4504	132	0	0
T25	5740	64	0	0
T61	0	18694	0	0
T77	0	600	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	1441197612	0	0
T1	5844	4760	0	0
T2	386408	382100	0	0
T3	1574256	1573924	0	0
T4	335112	315648	0	0
T5	1744384	1744032	0	0
T9	1604820	1604760	0	0
T22	141480	141140	0	0
T23	5148	4840	0	0
T24	4504	3680	0	0
T25	5740	5468	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	1441197612	0	0
T1	5844	4760	0	0
T2	386408	382100	0	0
T3	1574256	1573924	0	0
T4	335112	315648	0	0
T5	1744384	1744032	0	0
T9	1604820	1604760	0	0
T22	141480	141140	0	0
T23	5148	4840	0	0
T24	4504	3680	0	0
T25	5740	5468	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	349292419	0	0
T1	2922	132	0	0
T2	386408	142382	0	0
T3	1574256	497718	0	0
T4	335112	103152	0	0
T5	1744384	854600	0	0
T9	1604820	514658	0	0
T10	106146	18486	0	0
T15	0	239052	0	0
T16	0	844	0	0
T21	0	255794	0	0
T22	141480	1088	0	0
T23	5148	84	0	0
T24	4504	132	0	0
T25	5740	64	0	0
T61	0	18694	0	0
T77	0	600	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	172807980	0	0
T1	2922	522	0	0
T2	386408	4746	0	0
T3	1574256	200062	0	0
T4	335112	25024	0	0
T5	1744384	2990	0	0
T9	1604820	2109952	0	0
T10	106146	0	0	0
T15	0	86490	0	0
T16	0	1250	0	0
T21	0	1048576	0	0
T22	141480	2688	0	0
T23	5148	286	0	0
T24	4504	522	0	0
T25	5740	256	0	0
T42	0	76558	0	0
T61	0	1154	0	0
T77	0	1062	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	371869711	0	0
T1	2922	132	0	0
T2	386408	142382	0	0
T3	1574256	603638	0	0
T4	335112	103152	0	0
T5	1744384	854600	0	0
T9	1604820	514658	0	0
T10	106146	18486	0	0
T15	0	294748	0	0
T16	0	846	0	0
T21	0	255794	0	0
T22	141480	1088	0	0
T23	5148	84	0	0
T24	4504	132	0	0
T25	5740	64	0	0
T61	0	18694	0	0
T77	0	600	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	349292419	0	0
T1	2922	132	0	0
T2	386408	142382	0	0
T3	1574256	497718	0	0
T4	335112	103152	0	0
T5	1744384	854600	0	0
T9	1604820	514658	0	0
T10	106146	18486	0	0
T15	0	239052	0	0
T16	0	844	0	0
T21	0	255794	0	0
T22	141480	1088	0	0
T23	5148	84	0	0
T24	4504	132	0	0
T25	5740	64	0	0
T61	0	18694	0	0
T77	0	600	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	349292419	0	0
T1	2922	132	0	0
T2	386408	142382	0	0
T3	1574256	497718	0	0
T4	335112	103152	0	0
T5	1744384	854600	0	0
T9	1604820	514658	0	0
T10	106146	18486	0	0
T15	0	239052	0	0
T16	0	844	0	0
T21	0	255794	0	0
T22	141480	1088	0	0
T23	5148	84	0	0
T24	4504	132	0	0
T25	5740	64	0	0
T61	0	18694	0	0
T77	0	600	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	371869711	0	0
T1	2922	132	0	0
T2	386408	142382	0	0
T3	1574256	603638	0	0
T4	335112	103152	0	0
T5	1744384	854600	0	0
T9	1604820	514658	0	0
T10	106146	18486	0	0
T15	0	294748	0	0
T16	0	846	0	0
T21	0	255794	0	0
T22	141480	1088	0	0
T23	5148	84	0	0
T24	4504	132	0	0
T25	5740	64	0	0
T61	0	18694	0	0
T77	0	600	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1443873148	1441197612	0	0
T1	5844	4760	0	0
T2	386408	382100	0	0
T3	1574256	1573924	0	0
T4	335112	315648	0	0
T5	1744384	1744032	0	0
T9	1604820	1604760	0	0
T22	141480	141140	0	0
T23	5148	4840	0	0
T24	4504	3680	0	0
T25	5740	5468	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T23

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	360968287	360299403	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	360968287	89196946	0	0
GntImpliesValid_A	360968287	89196946	0	0
GrantKnown_A	360968287	360299403	0	0
IdxKnown_A	360968287	360299403	0	0
IndexIsCorrect_A	360968287	89196946	0	0
NoReadyValidNoGrant_A	360968287	44515425	0	0
Priority_A	360968287	95017122	0	0
ReadyAndValidImplyGrant_A	360968287	89196946	0	0
ReqAndReadyImplyGrant_A	360968287	89196946	0	0
ReqImpliesValid_A	360968287	95017122	0	0
ValidKnown_A	360968287	360299403	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	89196946	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	119266	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	89196946	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	119266	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	89196946	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	119266	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	44515425	0	0
T1	1461	261	0	0
T2	96602	2163	0	0
T3	393564	49181	0	0
T4	83778	12512	0	0
T5	436096	857	0	0
T9	401205	530688	0	0
T22	35370	1344	0	0
T23	1287	143	0	0
T24	1126	261	0	0
T25	1435	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	95017122	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	143852	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	89196946	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	119266	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	89196946	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	119266	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	95017122	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	143852	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T23

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	360968287	360299403	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	360968287	89196946	0	0
GntImpliesValid_A	360968287	89196946	0	0
GrantKnown_A	360968287	360299403	0	0
IdxKnown_A	360968287	360299403	0	0
IndexIsCorrect_A	360968287	89196946	0	0
NoReadyValidNoGrant_A	360968287	44515425	0	0
Priority_A	360968287	95017122	0	0
ReadyAndValidImplyGrant_A	360968287	89196946	0	0
ReqAndReadyImplyGrant_A	360968287	89196946	0	0
ReqImpliesValid_A	360968287	95017122	0	0
ValidKnown_A	360968287	360299403	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	89196946	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	119266	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	89196946	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	119266	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	89196946	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	119266	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	44515425	0	0
T1	1461	261	0	0
T2	96602	2163	0	0
T3	393564	49181	0	0
T4	83778	12512	0	0
T5	436096	857	0	0
T9	401205	530688	0	0
T22	35370	1344	0	0
T23	1287	143	0	0
T24	1126	261	0	0
T25	1435	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	95017122	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	143852	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	89196946	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	119266	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	89196946	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	119266	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	95017122	0	0
T1	1461	66	0	0
T2	96602	68929	0	0
T3	393564	143852	0	0
T4	83778	51576	0	0
T5	436096	213554	0	0
T9	401205	129432	0	0
T22	35370	544	0	0
T23	1287	42	0	0
T24	1126	66	0	0
T25	1435	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T3,T15,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T15,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T15,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T2,T3,T5
1	1	Covered	T3,T15,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T16
1	1	Covered	T2,T3,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T16
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T15,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T15,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	360968287	360299403	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	360968287	85449339	0	0
GntImpliesValid_A	360968287	85449339	0	0
GrantKnown_A	360968287	360299403	0	0
IdxKnown_A	360968287	360299403	0	0
IndexIsCorrect_A	360968287	85449339	0	0
NoReadyValidNoGrant_A	360968287	41888565	0	0
Priority_A	360968287	90917809	0	0
ReadyAndValidImplyGrant_A	360968287	85449339	0	0
ReqAndReadyImplyGrant_A	360968287	85449339	0	0
ReqImpliesValid_A	360968287	90917809	0	0
ValidKnown_A	360968287	360299403	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	85449339	0	0
T2	96602	2262	0	0
T3	393564	129593	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	119526	0	0
T16	0	422	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	85449339	0	0
T2	96602	2262	0	0
T3	393564	129593	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	119526	0	0
T16	0	422	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	85449339	0	0
T2	96602	2262	0	0
T3	393564	129593	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	119526	0	0
T16	0	422	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	41888565	0	0
T2	96602	210	0	0
T3	393564	50850	0	0
T4	83778	0	0	0
T5	436096	638	0	0
T9	401205	524288	0	0
T10	53073	0	0	0
T15	0	43245	0	0
T16	0	625	0	0
T21	0	524288	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T42	0	38279	0	0
T61	0	577	0	0
T77	0	531	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	90917809	0	0
T2	96602	2262	0	0
T3	393564	157967	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	147374	0	0
T16	0	423	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	85449339	0	0
T2	96602	2262	0	0
T3	393564	129593	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	119526	0	0
T16	0	422	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	85449339	0	0
T2	96602	2262	0	0
T3	393564	129593	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	119526	0	0
T16	0	422	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	90917809	0	0
T2	96602	2262	0	0
T3	393564	157967	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	147374	0	0
T16	0	423	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T3,T15,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T15,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T15,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T2,T3,T5
1	1	Covered	T3,T15,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T16
1	1	Covered	T2,T3,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T16
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T15,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T15,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	360968287	360299403	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	360968287	85449188	0	0
GntImpliesValid_A	360968287	85449188	0	0
GrantKnown_A	360968287	360299403	0	0
IdxKnown_A	360968287	360299403	0	0
IndexIsCorrect_A	360968287	85449188	0	0
NoReadyValidNoGrant_A	360968287	41888565	0	0
Priority_A	360968287	90917658	0	0
ReadyAndValidImplyGrant_A	360968287	85449188	0	0
ReqAndReadyImplyGrant_A	360968287	85449188	0	0
ReqImpliesValid_A	360968287	90917658	0	0
ValidKnown_A	360968287	360299403	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	85449188	0	0
T2	96602	2262	0	0
T3	393564	129593	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	119526	0	0
T16	0	422	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	85449188	0	0
T2	96602	2262	0	0
T3	393564	129593	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	119526	0	0
T16	0	422	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	85449188	0	0
T2	96602	2262	0	0
T3	393564	129593	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	119526	0	0
T16	0	422	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	41888565	0	0
T2	96602	210	0	0
T3	393564	50850	0	0
T4	83778	0	0	0
T5	436096	638	0	0
T9	401205	524288	0	0
T10	53073	0	0	0
T15	0	43245	0	0
T16	0	625	0	0
T21	0	524288	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T42	0	38279	0	0
T61	0	577	0	0
T77	0	531	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	90917658	0	0
T2	96602	2262	0	0
T3	393564	157967	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	147374	0	0
T16	0	423	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	85449188	0	0
T2	96602	2262	0	0
T3	393564	129593	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	119526	0	0
T16	0	422	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	85449188	0	0
T2	96602	2262	0	0
T3	393564	129593	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	119526	0	0
T16	0	422	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	90917658	0	0
T2	96602	2262	0	0
T3	393564	157967	0	0
T4	83778	0	0	0
T5	436096	213746	0	0
T9	401205	127897	0	0
T10	53073	9243	0	0
T15	0	147374	0	0
T16	0	423	0	0
T21	0	127897	0	0
T22	35370	0	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T61	0	9347	0	0
T77	0	300	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0