Unified Coverage Report :: Module :: flash_phy_erase

Module : flash_phy_erase

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase	97.22	100.00	88.89		100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase	97.22	100.00	88.89		100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.30	100.00	88.68		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	100.00	83.02		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_erase

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	39	3	3	100.00
ALWAYS	47	17	17	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
42	1	1
47	1	1
48	1	1
49	1	1
50	1	1
52	1	1
54	1	1
56	1	1
57	1	1
			MISSING_ELSE
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
73	1	1
74	1	1
75	1	1
			MISSING_ELSE
83	1	1
84	1	1
85	1	1

---

Cond Coverage for Module : flash_phy_erase

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T36
1	0	Covered	T4,T5,T9

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T37,T38,T164

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T36
1	1	Covered	T2,T5,T36

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T37,T38,T164
1	1	Covered	T37,T38,T164

---

FSM Coverage for Module : flash_phy_erase

Summary for FSM :: state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StEraseBusy	57	Covered	T2,T4,T5
StEraseIdle	68	Covered	T1,T2,T3
StEraseSuspend	65	Covered	T37,T38,T164

transitions	Line No.	Covered	Tests
StEraseBusy->StEraseIdle	68	Covered	T2,T4,T5
StEraseBusy->StEraseSuspend	65	Covered	T37,T38,T164
StEraseIdle->StEraseBusy	57	Covered	T2,T4,T5
StEraseSuspend->StEraseIdle	75	Covered	T37,T38,T164

---

Branch Coverage for Module : flash_phy_erase

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	39	2	2	100.00
CASE	52	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	52	case (state_q)
-2-:	56	if (((pg_erase_req_o || bk_erase_req_o) && ack_i))
-3-:	64	if ((suspend_req_i && ack_i))
-4-:	66	if (done_i)
-5-:	73	if (done_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StEraseIdle	1	-	-	-	Covered	T2,T4,T5
StEraseIdle	0	-	-	-	Covered	T1,T2,T3
StEraseBusy	-	1	-	-	Covered	T37,T38,T164
StEraseBusy	-	0	1	-	Covered	T2,T4,T5
StEraseBusy	-	0	0	-	Covered	T2,T4,T5
StEraseSuspend	-	-	-	1	Covered	T17,T37,T38
StEraseSuspend	-	-	-	0	Covered	T17
default	-	-	-	-	Covered	T17

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	39	3	3	100.00
ALWAYS	47	17	17	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
42	1	1
47	1	1
48	1	1
49	1	1
50	1	1
52	1	1
54	1	1
56	1	1
57	1	1
			MISSING_ELSE
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
73	1	1
74	1	1
75	1	1
			MISSING_ELSE
83	1	1
84	1	1
85	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T128
1	0	Covered	T4,T5,T9

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Not Covered
1	1	Covered	T37,T164,T39

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T128
1	1	Covered	T2,T5,T128

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T37,T38,T164
1	1	Covered	T37,T164,T39

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

Summary for FSM :: state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StEraseBusy	57	Covered	T2,T4,T5
StEraseIdle	68	Covered	T1,T2,T3
StEraseSuspend	65	Covered	T37,T164,T39

transitions	Line No.	Covered	Tests
StEraseBusy->StEraseIdle	68	Covered	T2,T4,T5
StEraseBusy->StEraseSuspend	65	Covered	T37,T164,T39
StEraseIdle->StEraseBusy	57	Covered	T2,T4,T5
StEraseSuspend->StEraseIdle	75	Covered	T37,T164,T39

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	39	2	2	100.00
CASE	52	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	52	case (state_q)
-2-:	56	if (((pg_erase_req_o || bk_erase_req_o) && ack_i))
-3-:	64	if ((suspend_req_i && ack_i))
-4-:	66	if (done_i)
-5-:	73	if (done_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StEraseIdle	1	-	-	-	Covered	T2,T4,T5
StEraseIdle	0	-	-	-	Covered	T1,T2,T3
StEraseBusy	-	1	-	-	Covered	T37,T164,T39
StEraseBusy	-	0	1	-	Covered	T2,T4,T5
StEraseBusy	-	0	0	-	Covered	T2,T4,T5
StEraseSuspend	-	-	-	1	Covered	T17,T37,T164
StEraseSuspend	-	-	-	0	Covered	T17
default	-	-	-	-	Covered	T17

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	39	3	3	100.00
ALWAYS	47	17	17	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
42	1	1
47	1	1
48	1	1
49	1	1
50	1	1
52	1	1
54	1	1
56	1	1
57	1	1
			MISSING_ELSE
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
73	1	1
74	1	1
75	1	1
			MISSING_ELSE
83	1	1
84	1	1
85	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T9,T21

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T36,T128
1	0	Covered	T5,T9,T21

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T21
1	0	Not Covered
1	1	Covered	T38,T164,T165

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T21
1	1	Covered	T5,T9,T21

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T36,T128
1	1	Covered	T5,T36,T128

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T21
1	0	Covered	T37,T38,T164
1	1	Covered	T38,T164,T165

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

Summary for FSM :: state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StEraseBusy	57	Covered	T5,T9,T21
StEraseIdle	68	Covered	T1,T2,T3
StEraseSuspend	65	Covered	T38,T164,T165

transitions	Line No.	Covered	Tests
StEraseBusy->StEraseIdle	68	Covered	T5,T9,T21
StEraseBusy->StEraseSuspend	65	Covered	T38,T164,T165
StEraseIdle->StEraseBusy	57	Covered	T5,T9,T21
StEraseSuspend->StEraseIdle	75	Covered	T38,T164,T165

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	39	2	2	100.00
CASE	52	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	52	case (state_q)
-2-:	56	if (((pg_erase_req_o || bk_erase_req_o) && ack_i))
-3-:	64	if ((suspend_req_i && ack_i))
-4-:	66	if (done_i)
-5-:	73	if (done_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StEraseIdle	1	-	-	-	Covered	T5,T9,T21
StEraseIdle	0	-	-	-	Covered	T1,T2,T3
StEraseBusy	-	1	-	-	Covered	T38,T164,T165
StEraseBusy	-	0	1	-	Covered	T5,T9,T21
StEraseBusy	-	0	0	-	Covered	T5,T9,T21
StEraseSuspend	-	-	-	1	Covered	T17,T38,T164
StEraseSuspend	-	-	-	0	Covered	T17
default	-	-	-	-	Covered	T17