Unified Coverage Report :: Module Instance :: tb.dut.u_to_prog_fifo.u_sramreqfifo

Module Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.47	85.71	38.46			85.71	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.63	94.44	54.84			81.25	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.89	100.00	65.22			85.71	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.48	100.00	66.67			77.78

Module Instance : tb.dut.u_to_prog_fifo.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.27	92.31	47.06			85.71	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.33	91.43	57.14			68.75	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.89	100.00	65.22			85.71	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	71.04	90.91	66.67			55.56

Module Instance : tb.dut.u_prog_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.73	97.12	86.40	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_to_rd_fifo.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.84	100.00	74.79			96.55	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	90.30	100.00	80.00			90.91

Module Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	72.22			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.84	100.00	74.79			96.55	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	90.30	100.00	80.00			90.91

Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.23	100.00	74.47	70.00		91.67	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.84	100.00	74.79			96.55	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	77.64	100.00	73.91	70.00		66.67

Module Instance : tb.dut.u_sw_rd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.67	95.12	88.64			90.91	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.73	97.12	86.40	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	92.40	92.59	100.00			84.62

Module Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.35	100.00	80.83			96.55	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.35	100.00	80.83			96.55	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	0	0
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101		unreachable
108	0	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Total	Covered	Percent
Conditions	13	5	38.46
Logical	13	5	38.46
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Not Covered
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	360968287	0	0	0
DepthKnown_A	360968287	360299403	0	0
RvalidKnown_A	360968287	360299403	0	0
WreadyKnown_A	360968287	360299403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	360968287	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	0	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		13	12	92.31
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	0	0
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100		unreachable
101	1	1
108	0	1
111	1	1
112		unreachable
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo

	Total	Covered	Percent
Conditions	17	8	47.06
Logical	17	8	47.06
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	130	1	1	100.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	360968287	0	0	0
DepthKnown_A	360968287	360299403	0	0
RvalidKnown_A	360968287	360299403	0	0
WreadyKnown_A	360968287	360299403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	360968287	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	0	0	0

Line Coverage for Instance : tb.dut.u_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_prog_fifo

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T36,T117
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_prog_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prog_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	360968287	137335931	0	0
DepthKnown_A	360968287	360299403	0	0
RvalidKnown_A	360968287	360299403	0	0
WreadyKnown_A	360968287	360299403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	360968287	137335931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	137335931	0	0
T2	96602	4881	0	0
T3	393564	277933	0	0
T4	83778	22344	0	0
T5	436096	28103	0	0
T9	401205	217539	0	0
T10	53073	22732	0	0
T15	0	260897	0	0
T21	0	217539	0	0
T22	35370	6528	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	1180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	137335931	0	0
T2	96602	4881	0	0
T3	393564	277933	0	0
T4	83778	22344	0	0
T5	436096	28103	0	0
T9	401205	217539	0	0
T10	53073	22732	0	0
T15	0	260897	0	0
T21	0	217539	0	0
T22	35370	6528	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	1180	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T16,T26
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	360968287	5606227	0	0
DepthKnown_A	360968287	360299403	0	0
RvalidKnown_A	360968287	360299403	0	0
WreadyKnown_A	360968287	360299403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	360968287	5606227	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	5606227	0	0
T2	96602	250	0	0
T3	393564	11344	0	0
T4	83778	1608	0	0
T5	436096	1043	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	11416	0	0
T16	0	552	0	0
T22	35370	4096	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	92	0	0
T27	0	18544	0	0
T61	0	230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	5606227	0	0
T2	96602	250	0	0
T3	393564	11344	0	0
T4	83778	1608	0	0
T5	436096	1043	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	11416	0	0
T16	0	552	0	0
T22	35370	4096	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	92	0	0
T27	0	18544	0	0
T61	0	230	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	360968287	3304990	0	0
DepthKnown_A	360968287	360299403	0	0
RvalidKnown_A	360968287	360299403	0	0
WreadyKnown_A	360968287	360299403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	360968287	3304990	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	3304990	0	0
T2	96602	250	0	0
T3	393564	11344	0	0
T4	83778	1608	0	0
T5	436096	1043	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	11416	0	0
T16	0	552	0	0
T22	35370	4096	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	92	0	0
T27	0	4096	0	0
T61	0	230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	3304990	0	0
T2	96602	250	0	0
T3	393564	11344	0	0
T4	83778	1608	0	0
T5	436096	1043	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	11416	0	0
T16	0	552	0	0
T22	35370	4096	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	92	0	0
T27	0	4096	0	0
T61	0	230	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T27,T50,T118
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T16,T26
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T27,T50,T118
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	360968287	5606227	0	0
DepthKnown_A	360968287	360299403	0	0
RvalidKnown_A	360968287	360299403	0	0
WreadyKnown_A	360968287	360299403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	360968287	5606227	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	5606227	0	0
T2	96602	250	0	0
T3	393564	11344	0	0
T4	83778	1608	0	0
T5	436096	1043	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	11416	0	0
T16	0	552	0	0
T22	35370	4096	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	92	0	0
T27	0	18544	0	0
T61	0	230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	5606227	0	0
T2	96602	250	0	0
T3	393564	11344	0	0
T4	83778	1608	0	0
T5	436096	1043	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	11416	0	0
T16	0	552	0	0
T22	35370	4096	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	92	0	0
T27	0	18544	0	0
T61	0	230	0	0

Line Coverage for Instance : tb.dut.u_sw_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sw_rd_fifo

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T27,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sw_rd_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sw_rd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	360968287	52458158	0	0
DepthKnown_A	360968287	360299403	0	0
RvalidKnown_A	360968287	360299403	0	0
WreadyKnown_A	360968287	360299403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	360968287	52458158	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	52458158	0	0
T2	96602	1672	0	0
T3	393564	43846	0	0
T4	83778	6794	0	0
T5	436096	4330	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	43963	0	0
T16	0	2298	0	0
T22	35370	16393	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	1273	0	0
T27	0	86289	0	0
T61	0	974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	52458158	0	0
T2	96602	1672	0	0
T3	393564	43846	0	0
T4	83778	6794	0	0
T5	436096	4330	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	43963	0	0
T16	0	2298	0	0
T22	35370	16393	0	0
T23	1287	0	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	1273	0	0
T27	0	86289	0	0
T61	0	974	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T23

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T23

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T23
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T23

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T23
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T23

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	360968287	31666184	0	0
DepthKnown_A	360968287	360299403	0	0
RvalidKnown_A	360968287	360299403	0	0
WreadyKnown_A	360968287	360299403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	360968287	31666184	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	31666184	0	0
T2	96602	162	0	0
T3	393564	130104	0	0
T4	83778	0	0	0
T5	436096	0	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	125168	0	0
T16	0	736	0	0
T22	35370	0	0	0
T23	1287	15	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	397	0	0
T33	0	8	0	0
T42	0	44753	0	0
T61	0	53	0	0
T77	0	884	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	31666184	0	0
T2	96602	162	0	0
T3	393564	130104	0	0
T4	83778	0	0	0
T5	436096	0	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	125168	0	0
T16	0	736	0	0
T22	35370	0	0	0
T23	1287	15	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	397	0	0
T33	0	8	0	0
T42	0	44753	0	0
T61	0	53	0	0
T77	0	884	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T23

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T23

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T23
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T23

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T23
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T23

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	360968287	30251532	0	0
DepthKnown_A	360968287	360299403	0	0
RvalidKnown_A	360968287	360299403	0	0
WreadyKnown_A	360968287	360299403	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	360968287	30251532	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	30251532	0	0
T2	96602	60	0	0
T3	393564	130104	0	0
T4	83778	0	0	0
T5	436096	0	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	125168	0	0
T16	0	526	0	0
T22	35370	0	0	0
T23	1287	15	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	146	0	0
T33	0	8	0	0
T42	0	44753	0	0
T61	0	53	0	0
T77	0	884	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	360299403	0	0
T1	1461	1190	0	0
T2	96602	95525	0	0
T3	393564	393481	0	0
T4	83778	78912	0	0
T5	436096	436008	0	0
T9	401205	401190	0	0
T22	35370	35285	0	0
T23	1287	1210	0	0
T24	1126	920	0	0
T25	1435	1367	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	360968287	30251532	0	0
T2	96602	60	0	0
T3	393564	130104	0	0
T4	83778	0	0	0
T5	436096	0	0	0
T9	401205	0	0	0
T10	53073	0	0	0
T15	0	125168	0	0
T16	0	526	0	0
T22	35370	0	0	0
T23	1287	15	0	0
T24	1126	0	0	0
T25	1435	0	0	0
T26	0	146	0	0
T33	0	8	0	0
T42	0	44753	0	0
T61	0	53	0	0
T77	0	884	0	0