Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_buf
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_buf_0/prim_buf.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_buf
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[4].gen_bits[0].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[4].gen_bits[1].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[4].gen_bits[2].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[4].gen_bits[3].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[5].gen_bits[0].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[5].gen_bits[1].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[5].gen_bits[2].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[5].gen_bits[3].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[6].gen_bits[0].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[6].gen_bits[1].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[6].gen_bits[2].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[6].gen_bits[3].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[7].gen_bits[0].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[7].gen_bits[1].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[7].gen_bits[2].u_prim_buf
tb.dut.u_disable_buf.gen_buffs[7].gen_bits[3].u_prim_buf
tb.dut.u_exec_en_buf.u_secure_anchor_buf
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].u_req_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].u_req_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].u_req_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].u_req_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].u_req_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].u_req_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_intg_buf.u_secure_anchor_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].u_req_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].u_req_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_intg_buf.u_secure_anchor_buf



Module Instance : tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_sec_buf.u_prim_sec_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_exec_en_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_exec_en_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].u_req_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].u_req_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].u_req_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].u_req_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].u_req_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.67 90.00 40.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.67 90.00 40.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 0.00 0.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.67 90.00 40.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 0.00 0.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].u_req_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.67 90.00 40.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.67 90.00 40.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 0.00 0.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.67 90.00 40.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 0.00 0.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_intg_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_intg_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].u_req_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 90.00 100.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 90.00 100.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 0.00 0.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 90.00 100.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 0.00 0.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].u_req_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 90.00 100.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 90.00 100.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 0.00 0.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 90.00 100.00 100.00 u_host_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 0.00 0.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_intg_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_intg_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00

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