Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	238643	1		T1	1		T2	2		T3	1
all_values[1]	238643	1		T1	1		T2	2		T3	1
all_values[2]	238643	1		T1	1		T2	2		T3	1
all_values[3]	238643	1		T1	1		T2	2		T3	1
all_values[4]	238643	1		T1	1		T2	2		T3	1
all_values[5]	238643	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	482715	1		T1	6		T2	12		T3	6
auto[1]	949143	1		T12	8832		T13	8624		T14	14880

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	695993	1		T1	4		T2	7		T3	4
auto[1]	735865	1		T1	2		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	238473	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	170	1		T234	4		T235	4		T236	7
all_values[1]	auto[0]	auto[1]	238467	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	176	1		T234	6		T235	5		T236	4
all_values[2]	auto[0]	auto[0]	1396	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	63	1		T234	2		T236	2		T347	1
all_values[2]	auto[1]	auto[0]	237127	1		T12	2208		T13	2156		T14	3720
all_values[2]	auto[1]	auto[1]	57	1		T234	2		T236	1		T348	1
all_values[3]	auto[0]	auto[0]	1393	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	51	1		T234	1		T236	2		T347	1
all_values[3]	auto[1]	auto[0]	54900	1		T12	736		T13	1078		T14	1206
all_values[3]	auto[1]	auto[1]	182299	1		T12	1472		T13	1078		T14	2514
all_values[4]	auto[0]	auto[0]	985	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	461	1		T2	1		T5	1		T6	1
all_values[4]	auto[1]	auto[0]	161715	1		T12	1472		T13	1078		T14	2463
all_values[4]	auto[1]	auto[1]	75482	1		T12	736		T13	1078		T14	1257
all_values[5]	auto[0]	auto[0]	1330	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	96	1		T89	1		T50	1		T47	1
all_values[5]	auto[1]	auto[0]	237147	1		T12	2208		T13	2156		T14	3720
all_values[5]	auto[1]	auto[1]	70	1		T234	3		T235	1		T236	2