Unified Coverage Report

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmRdFifoRptrCheck_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmRdFifoWptrCheck_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	348705990	0	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	348705990	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	348705990	0	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	348705990	0	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	348705990	0	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	348705990	0	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	348705990	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	348705990	0	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	348705990	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	348705990	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	348705990	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	348705990	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	348705990	0	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	348705990	0	0	870
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	348705990	0	0	870
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	348705990	0	0	870
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	348705990	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	348705990	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	348705990	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	348705990	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	348705990	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	348705990	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	348705990	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	348705990	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	875	875	0	0
tb.dut.FlashAddrKnown_A	0	0	348705990	252111931	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	348705990	348098510	0	0
tb.dut.FlashKnownO_A	0	0	348705990	348098510	0	0
tb.dut.FlashProgKnown_A	0	0	348705990	135539916	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	348705990	348098510	0	0
tb.dut.IntrErrO_A	0	0	348705990	348098510	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	348705990	348098510	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	348705990	348098510	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	348705990	348098510	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	348705990	348098510	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	348705990	348098510	0	0
tb.dut.MemRspPayLoad_A	0	0	348705990	4058991	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	348705990	348098510	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	348705990	348098510	0	0
tb.dut.MemTlDValidKnownO_A	0	0	348705990	348098510	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	348705990	348098510	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	348705990	348098510	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	348705990	348098510	0	0
tb.dut.RspPayLoad_A	0	0	348705990	35057881	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	348705990	348098510	0	0
tb.dut.TdoEnIsOne_A	0	0	348705990	348098510	0	0
tb.dut.TdoKnown_A	0	0	348705990	348098510	0	0
tb.dut.TlAReadyKnownO_A	0	0	348705990	348098510	0	0
tb.dut.TlDValidKnownO_A	0	0	348705990	348098510	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	351747806	3442	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	351747806	3481	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	351747806	4360	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	351747806	4232	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	351747806	3593	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	351747806	5324	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	351747806	4743	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	351747806	4487	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	351747806	4548	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	351747806	5191	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	351747806	4793	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	351747806	5121	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	351747806	3732	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	351747806	3765	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	351747806	2902	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	351747806	2802	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	351747806	3868	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	351747806	3359	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	351747806	3699	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	351747806	3899	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	351747806	3384	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	351747806	3475	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	351747806	5425	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	351747806	2448	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	351747806	4105	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	351747806	4556	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	351747806	4098	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	351747806	3350	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	351747806	4952	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	351747806	5406	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	351747806	4839	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	351747806	4926	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	351747806	4644	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	351747806	4810	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	351747806	3614	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	351747806	5215	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	351747806	4742	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	351747806	4795	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	351747806	4049	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	351747806	3366	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	351747806	3796	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	351747806	3449	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	351747806	4020	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	351747806	3451	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	351747806	3275	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	351747806	3484	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	351747806	2675	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	351747806	3474	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	351747806	4092	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	351747806	2800	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	351747806	4278	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	351747806	4776	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	351747806	3380	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	351747806	3392	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	351747806	2392	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	351747806	4518	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	351747806	3747	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	351747806	3459	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	351747806	2854	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	351747806	3644	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	351747806	3546	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	351747806	3628	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	351747806	4100	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	351747806	3619	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	351747806	3510	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	351747806	4034	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	351747806	3720	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	351747806	3226	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	351747806	3104	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	351747806	4216	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	351747806	4191	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	351747806	4381	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	351747806	4893	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	351747806	5381	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	351747806	4824	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	351747806	5055	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	351747806	4511	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	351747806	1798	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	351747806	2834	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	351747806	3841	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	351747806	3286	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	351747806	4010	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	351747806	2861	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	351747806	3354	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	351747806	3996	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	351747806	1908	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	351747806	3318	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	351747725	31755576	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	351747725	351051036	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	351747725	351051036	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	351747725	36031537	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	351747725	351051036	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	351747725	351051036	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
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tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
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tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
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tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0
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tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	1085	1085	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	992	0	10
Category 0	992	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	992	0	10
Severity 0	992	0	10

	NUMBER	PERCENT
Total Number	992	100.00
Uncovered	50	5.04
Success	942	94.96
Failure	0	0.00
Incomplete	15	1.51
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	0	0.00
All Matches	10	100.00
First Matches	10	100.00