Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T6 |
1 |
|
T43 |
10 |
|
T130 |
7 |
| others[1] |
222 |
1 |
|
T43 |
8 |
|
T130 |
6 |
|
T131 |
1 |
| others[2] |
201 |
1 |
|
T43 |
9 |
|
T130 |
10 |
|
T213 |
1 |
| others[3] |
371 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T43 |
16 |
| false |
126 |
1 |
|
T43 |
6 |
|
T130 |
6 |
|
T214 |
1 |
| true |
11768 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7424 |
1 |
|
T1 |
2 |
|
T3 |
8 |
|
T5 |
1 |
| others[1] |
1238 |
1 |
|
T2 |
1 |
|
T3 |
14 |
|
T10 |
19 |
| others[2] |
1234 |
1 |
|
T3 |
13 |
|
T10 |
11 |
|
T42 |
2 |
| others[3] |
2031 |
1 |
|
T3 |
16 |
|
T10 |
25 |
|
T26 |
1 |
| false |
661 |
1 |
|
T3 |
11 |
|
T5 |
1 |
|
T10 |
9 |
| true |
318 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7494 |
1 |
|
T1 |
2 |
|
T3 |
16 |
|
T15 |
48 |
| others[1] |
1223 |
1 |
|
T3 |
7 |
|
T5 |
1 |
|
T10 |
21 |
| others[2] |
1238 |
1 |
|
T3 |
21 |
|
T10 |
18 |
|
T26 |
1 |
| others[3] |
2017 |
1 |
|
T3 |
15 |
|
T5 |
1 |
|
T10 |
25 |
| false |
639 |
1 |
|
T2 |
1 |
|
T3 |
3 |
|
T10 |
9 |
| true |
295 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T43 |
1 |
|
T130 |
2 |
|
T214 |
1 |
| others[1] |
127 |
1 |
|
T43 |
6 |
|
T130 |
3 |
|
T133 |
3 |
| others[2] |
108 |
1 |
|
T43 |
4 |
|
T130 |
5 |
|
T129 |
1 |
| others[3] |
172 |
1 |
|
T5 |
1 |
|
T43 |
5 |
|
T130 |
5 |
| false |
63 |
1 |
|
T5 |
1 |
|
T43 |
4 |
|
T130 |
1 |
| true |
12336 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T43 |
7 |
|
T130 |
9 |
|
T132 |
1 |
| others[1] |
211 |
1 |
|
T43 |
9 |
|
T130 |
10 |
|
T92 |
1 |
| others[2] |
234 |
1 |
|
T43 |
6 |
|
T11 |
1 |
|
T130 |
8 |
| others[3] |
409 |
1 |
|
T2 |
1 |
|
T43 |
23 |
|
T130 |
16 |
| false |
105 |
1 |
|
T16 |
1 |
|
T43 |
1 |
|
T130 |
3 |
| true |
11737 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7228 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
4 |
| others[1] |
981 |
1 |
|
T3 |
5 |
|
T5 |
1 |
|
T10 |
16 |
| others[2] |
1111 |
1 |
|
T3 |
6 |
|
T10 |
14 |
|
T42 |
3 |
| others[3] |
1717 |
1 |
|
T3 |
6 |
|
T4 |
1 |
|
T10 |
29 |
| false |
537 |
1 |
|
T3 |
2 |
|
T6 |
1 |
|
T10 |
8 |
| true |
1332 |
1 |
|
T3 |
39 |
|
T26 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T16 |
1 |
|
T43 |
8 |
|
T130 |
9 |
| others[1] |
243 |
1 |
|
T6 |
1 |
|
T43 |
9 |
|
T130 |
9 |
| others[2] |
220 |
1 |
|
T43 |
9 |
|
T130 |
10 |
|
T90 |
2 |
| others[3] |
384 |
1 |
|
T17 |
1 |
|
T43 |
8 |
|
T130 |
22 |
| false |
126 |
1 |
|
T43 |
8 |
|
T130 |
3 |
|
T133 |
3 |
| true |
11722 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T43 |
6 |
|
T130 |
14 |
|
T18 |
2 |
| others[1] |
214 |
1 |
|
T43 |
7 |
|
T130 |
13 |
|
T192 |
1 |
| others[2] |
222 |
1 |
|
T16 |
1 |
|
T43 |
14 |
|
T130 |
12 |
| others[3] |
371 |
1 |
|
T2 |
1 |
|
T43 |
17 |
|
T130 |
17 |
| false |
132 |
1 |
|
T43 |
5 |
|
T130 |
9 |
|
T133 |
5 |
| true |
11750 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7426 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
13 |
| others[1] |
1254 |
1 |
|
T3 |
12 |
|
T10 |
22 |
|
T26 |
1 |
| others[2] |
1284 |
1 |
|
T3 |
13 |
|
T5 |
1 |
|
T10 |
18 |
| others[3] |
1971 |
1 |
|
T3 |
18 |
|
T5 |
1 |
|
T10 |
18 |
| false |
643 |
1 |
|
T3 |
6 |
|
T10 |
11 |
|
T43 |
13 |
| true |
328 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T3 |
13 |
|
T10 |
13 |
|
T42 |
5 |
| others[1] |
1232 |
1 |
|
T3 |
9 |
|
T5 |
1 |
|
T10 |
16 |
| others[2] |
1199 |
1 |
|
T3 |
13 |
|
T10 |
17 |
|
T16 |
1 |
| others[3] |
2037 |
1 |
|
T2 |
1 |
|
T3 |
21 |
|
T10 |
22 |
| false |
672 |
1 |
|
T3 |
6 |
|
T5 |
1 |
|
T6 |
1 |
| true |
299 |
1 |
|
T4 |
1 |
|
T21 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T17 |
1 |
|
T43 |
3 |
|
T130 |
5 |
| others[1] |
104 |
1 |
|
T2 |
1 |
|
T43 |
4 |
|
T130 |
3 |
| others[2] |
98 |
1 |
|
T16 |
1 |
|
T43 |
5 |
|
T130 |
6 |
| others[3] |
164 |
1 |
|
T5 |
1 |
|
T43 |
4 |
|
T130 |
7 |
| false |
57 |
1 |
|
T5 |
1 |
|
T43 |
2 |
|
T92 |
1 |
| true |
6160 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T43 |
10 |
|
T130 |
8 |
|
T33 |
1 |
| others[1] |
228 |
1 |
|
T43 |
7 |
|
T11 |
1 |
|
T130 |
10 |
| others[2] |
221 |
1 |
|
T43 |
8 |
|
T130 |
8 |
|
T131 |
1 |
| others[3] |
357 |
1 |
|
T2 |
1 |
|
T43 |
19 |
|
T130 |
18 |
| false |
141 |
1 |
|
T5 |
1 |
|
T43 |
6 |
|
T130 |
6 |
| true |
5508 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
995 |
1 |
|
T3 |
5 |
|
T5 |
1 |
|
T10 |
13 |
| others[1] |
1036 |
1 |
|
T3 |
6 |
|
T5 |
1 |
|
T10 |
17 |
| others[2] |
1058 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T10 |
9 |
| others[3] |
1741 |
1 |
|
T3 |
17 |
|
T10 |
32 |
|
T42 |
4 |
| false |
536 |
1 |
|
T3 |
1 |
|
T10 |
10 |
|
T16 |
1 |
| true |
1319 |
1 |
|
T3 |
28 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
194 |
1 |
|
T43 |
13 |
|
T130 |
17 |
|
T34 |
1 |
| others[1] |
248 |
1 |
|
T43 |
14 |
|
T130 |
9 |
|
T129 |
1 |
| others[2] |
214 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T43 |
9 |
| others[3] |
363 |
1 |
|
T17 |
1 |
|
T43 |
13 |
|
T130 |
22 |
| false |
116 |
1 |
|
T43 |
3 |
|
T130 |
4 |
|
T255 |
1 |
| true |
5550 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T43 |
8 |
|
T130 |
8 |
|
T18 |
1 |
| others[1] |
213 |
1 |
|
T2 |
1 |
|
T43 |
12 |
|
T130 |
7 |
| others[2] |
216 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T43 |
14 |
| others[3] |
342 |
1 |
|
T43 |
15 |
|
T130 |
12 |
|
T50 |
1 |
| false |
123 |
1 |
|
T43 |
1 |
|
T130 |
4 |
|
T132 |
1 |
| true |
5558 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T3 |
19 |
|
T10 |
11 |
|
T42 |
2 |
| others[1] |
1214 |
1 |
|
T3 |
12 |
|
T5 |
1 |
|
T10 |
16 |
| others[2] |
1236 |
1 |
|
T3 |
9 |
|
T5 |
1 |
|
T10 |
16 |
| others[3] |
2010 |
1 |
|
T2 |
1 |
|
T3 |
17 |
|
T10 |
31 |
| false |
632 |
1 |
|
T3 |
5 |
|
T10 |
7 |
|
T42 |
2 |
| true |
320 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T42 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1203 |
1 |
|
T3 |
10 |
|
T5 |
1 |
|
T6 |
1 |
| others[1] |
1279 |
1 |
|
T2 |
1 |
|
T3 |
20 |
|
T10 |
22 |
| others[2] |
1191 |
1 |
|
T3 |
12 |
|
T10 |
11 |
|
T42 |
2 |
| others[3] |
2087 |
1 |
|
T3 |
18 |
|
T5 |
1 |
|
T10 |
29 |
| false |
622 |
1 |
|
T3 |
2 |
|
T10 |
7 |
|
T26 |
1 |
| true |
303 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T43 |
5 |
|
T130 |
2 |
|
T213 |
2 |
| others[1] |
94 |
1 |
|
T5 |
1 |
|
T43 |
6 |
|
T214 |
1 |
| others[2] |
111 |
1 |
|
T43 |
1 |
|
T130 |
9 |
|
T214 |
1 |
| others[3] |
185 |
1 |
|
T2 |
1 |
|
T43 |
7 |
|
T130 |
5 |
| false |
50 |
1 |
|
T5 |
1 |
|
T43 |
5 |
|
T33 |
1 |
| true |
6134 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T5 |
1 |
|
T43 |
4 |
|
T130 |
10 |
| others[1] |
220 |
1 |
|
T43 |
8 |
|
T130 |
7 |
|
T47 |
1 |
| others[2] |
246 |
1 |
|
T16 |
1 |
|
T43 |
11 |
|
T130 |
12 |
| others[3] |
346 |
1 |
|
T17 |
1 |
|
T43 |
13 |
|
T11 |
1 |
| false |
119 |
1 |
|
T43 |
4 |
|
T130 |
2 |
|
T50 |
1 |
| true |
5509 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1034 |
1 |
|
T3 |
6 |
|
T10 |
19 |
|
T42 |
1 |
| others[1] |
992 |
1 |
|
T3 |
6 |
|
T10 |
12 |
|
T42 |
2 |
| others[2] |
1017 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T5 |
1 |
| others[3] |
1777 |
1 |
|
T3 |
11 |
|
T10 |
26 |
|
T16 |
1 |
| false |
500 |
1 |
|
T3 |
4 |
|
T5 |
1 |
|
T10 |
11 |
| true |
1365 |
1 |
|
T3 |
30 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T43 |
8 |
|
T130 |
8 |
|
T213 |
1 |
| others[1] |
220 |
1 |
|
T43 |
8 |
|
T130 |
7 |
|
T34 |
1 |
| others[2] |
210 |
1 |
|
T16 |
1 |
|
T43 |
10 |
|
T130 |
13 |
| others[3] |
348 |
1 |
|
T43 |
9 |
|
T130 |
12 |
|
T129 |
1 |
| false |
141 |
1 |
|
T43 |
7 |
|
T130 |
8 |
|
T133 |
3 |
| true |
5551 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T5 |
1 |
|
T43 |
9 |
|
T130 |
12 |
| others[1] |
192 |
1 |
|
T43 |
12 |
|
T130 |
8 |
|
T129 |
1 |
| others[2] |
240 |
1 |
|
T6 |
1 |
|
T43 |
9 |
|
T130 |
8 |
| others[3] |
362 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T43 |
14 |
| false |
109 |
1 |
|
T43 |
8 |
|
T130 |
8 |
|
T192 |
1 |
| true |
5538 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1197 |
1 |
|
T3 |
11 |
|
T5 |
2 |
|
T10 |
15 |
| others[1] |
1248 |
1 |
|
T3 |
10 |
|
T10 |
17 |
|
T9 |
1 |
| others[2] |
1191 |
1 |
|
T3 |
8 |
|
T10 |
15 |
|
T42 |
1 |
| others[3] |
2059 |
1 |
|
T2 |
1 |
|
T3 |
22 |
|
T10 |
26 |
| false |
671 |
1 |
|
T3 |
11 |
|
T10 |
8 |
|
T42 |
1 |
| true |
319 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1281 |
1 |
|
T3 |
13 |
|
T10 |
20 |
|
T42 |
3 |
| others[1] |
1229 |
1 |
|
T2 |
1 |
|
T3 |
9 |
|
T10 |
12 |
| others[2] |
1222 |
1 |
|
T3 |
12 |
|
T10 |
16 |
|
T42 |
4 |
| others[3] |
2045 |
1 |
|
T3 |
22 |
|
T5 |
2 |
|
T10 |
23 |
| false |
618 |
1 |
|
T3 |
6 |
|
T10 |
10 |
|
T42 |
1 |
| true |
290 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T130 |
4 |
| others[1] |
90 |
1 |
|
T5 |
1 |
|
T43 |
2 |
|
T130 |
3 |
| others[2] |
115 |
1 |
|
T43 |
6 |
|
T130 |
5 |
|
T50 |
1 |
| others[3] |
160 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T43 |
4 |
| false |
42 |
1 |
|
T43 |
1 |
|
T130 |
3 |
|
T213 |
1 |
| true |
6175 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T6 |
1 |
|
T43 |
4 |
|
T130 |
6 |
| others[1] |
249 |
1 |
|
T43 |
17 |
|
T11 |
1 |
|
T130 |
17 |
| others[2] |
221 |
1 |
|
T17 |
1 |
|
T43 |
12 |
|
T130 |
6 |
| others[3] |
415 |
1 |
|
T5 |
1 |
|
T43 |
11 |
|
T130 |
17 |
| false |
126 |
1 |
|
T43 |
9 |
|
T130 |
5 |
|
T133 |
3 |
| true |
5458 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1057 |
1 |
|
T3 |
8 |
|
T5 |
1 |
|
T10 |
18 |
| others[1] |
1039 |
1 |
|
T3 |
3 |
|
T6 |
1 |
|
T10 |
19 |
| others[2] |
1023 |
1 |
|
T3 |
3 |
|
T10 |
10 |
|
T42 |
4 |
| others[3] |
1712 |
1 |
|
T2 |
1 |
|
T3 |
10 |
|
T10 |
28 |
| false |
558 |
1 |
|
T3 |
3 |
|
T5 |
1 |
|
T10 |
6 |
| true |
1296 |
1 |
|
T3 |
35 |
|
T4 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T5 |
2 |
|
T6 |
1 |
|
T43 |
9 |
| others[1] |
205 |
1 |
|
T17 |
1 |
|
T43 |
5 |
|
T130 |
10 |
| others[2] |
217 |
1 |
|
T43 |
13 |
|
T130 |
12 |
|
T131 |
1 |
| others[3] |
385 |
1 |
|
T2 |
1 |
|
T43 |
19 |
|
T130 |
16 |
| false |
109 |
1 |
|
T43 |
4 |
|
T133 |
6 |
|
T392 |
1 |
| true |
5536 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T43 |
12 |
|
T130 |
10 |
|
T133 |
12 |
| others[1] |
231 |
1 |
|
T43 |
10 |
|
T130 |
7 |
|
T33 |
1 |
| others[2] |
200 |
1 |
|
T43 |
6 |
|
T130 |
8 |
|
T131 |
1 |
| others[3] |
384 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T43 |
18 |
| false |
94 |
1 |
|
T43 |
3 |
|
T130 |
2 |
|
T18 |
1 |
| true |
5557 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T3 |
15 |
|
T10 |
14 |
|
T9 |
1 |
| others[1] |
1187 |
1 |
|
T3 |
15 |
|
T5 |
1 |
|
T10 |
18 |
| others[2] |
1240 |
1 |
|
T3 |
11 |
|
T10 |
18 |
|
T42 |
2 |
| others[3] |
2060 |
1 |
|
T2 |
1 |
|
T3 |
16 |
|
T5 |
1 |
| false |
655 |
1 |
|
T3 |
5 |
|
T10 |
9 |
|
T42 |
2 |
| true |
313 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T42 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T3 |
16 |
|
T5 |
1 |
|
T10 |
13 |
| others[1] |
1228 |
1 |
|
T3 |
13 |
|
T5 |
1 |
|
T10 |
13 |
| others[2] |
1197 |
1 |
|
T3 |
9 |
|
T10 |
16 |
|
T42 |
5 |
| others[3] |
2098 |
1 |
|
T2 |
1 |
|
T3 |
18 |
|
T10 |
25 |
| false |
616 |
1 |
|
T3 |
6 |
|
T10 |
14 |
|
T42 |
1 |
| true |
293 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |