Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T6 |
1 |
|
T43 |
6 |
|
T130 |
2 |
| others[1] |
101 |
1 |
|
T43 |
3 |
|
T130 |
3 |
|
T129 |
1 |
| others[2] |
108 |
1 |
|
T2 |
1 |
|
T43 |
4 |
|
T130 |
6 |
| others[3] |
160 |
1 |
|
T5 |
1 |
|
T43 |
4 |
|
T130 |
8 |
| false |
55 |
1 |
|
T5 |
1 |
|
T43 |
2 |
|
T130 |
1 |
| true |
6148 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T43 |
12 |
| others[1] |
207 |
1 |
|
T5 |
1 |
|
T43 |
13 |
|
T130 |
5 |
| others[2] |
245 |
1 |
|
T43 |
7 |
|
T130 |
9 |
|
T213 |
1 |
| others[3] |
363 |
1 |
|
T43 |
18 |
|
T130 |
18 |
|
T89 |
1 |
| false |
119 |
1 |
|
T43 |
4 |
|
T130 |
4 |
|
T214 |
1 |
| true |
5532 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1080 |
1 |
|
T3 |
9 |
|
T5 |
1 |
|
T10 |
20 |
| others[1] |
1007 |
1 |
|
T2 |
1 |
|
T3 |
4 |
|
T10 |
15 |
| others[2] |
1026 |
1 |
|
T3 |
9 |
|
T10 |
18 |
|
T42 |
4 |
| others[3] |
1684 |
1 |
|
T3 |
8 |
|
T5 |
1 |
|
T10 |
16 |
| false |
588 |
1 |
|
T3 |
8 |
|
T10 |
12 |
|
T9 |
1 |
| true |
1300 |
1 |
|
T3 |
24 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T43 |
7 |
|
T130 |
11 |
|
T133 |
11 |
| others[1] |
231 |
1 |
|
T43 |
8 |
|
T130 |
11 |
|
T89 |
1 |
| others[2] |
243 |
1 |
|
T43 |
17 |
|
T130 |
8 |
|
T92 |
1 |
| others[3] |
348 |
1 |
|
T17 |
1 |
|
T43 |
12 |
|
T130 |
11 |
| false |
126 |
1 |
|
T43 |
3 |
|
T130 |
5 |
|
T33 |
1 |
| true |
5522 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T6 |
1 |
|
T43 |
16 |
|
T130 |
9 |
| others[1] |
213 |
1 |
|
T43 |
5 |
|
T130 |
11 |
|
T214 |
1 |
| others[2] |
199 |
1 |
|
T5 |
1 |
|
T43 |
11 |
|
T130 |
8 |
| others[3] |
349 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T43 |
18 |
| false |
115 |
1 |
|
T43 |
3 |
|
T130 |
5 |
|
T129 |
1 |
| true |
5585 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T3 |
11 |
|
T10 |
9 |
|
T26 |
1 |
| others[1] |
1229 |
1 |
|
T3 |
9 |
|
T5 |
2 |
|
T10 |
16 |
| others[2] |
1205 |
1 |
|
T3 |
11 |
|
T10 |
23 |
|
T42 |
4 |
| others[3] |
2054 |
1 |
|
T2 |
1 |
|
T3 |
22 |
|
T10 |
20 |
| false |
629 |
1 |
|
T3 |
9 |
|
T10 |
13 |
|
T42 |
2 |
| true |
331 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T3 |
13 |
|
T10 |
12 |
|
T42 |
1 |
| others[1] |
1258 |
1 |
|
T3 |
13 |
|
T10 |
19 |
|
T42 |
5 |
| others[2] |
1211 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T5 |
2 |
| others[3] |
2061 |
1 |
|
T3 |
22 |
|
T10 |
20 |
|
T26 |
1 |
| false |
631 |
1 |
|
T3 |
7 |
|
T10 |
10 |
|
T42 |
3 |
| true |
294 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T43 |
4 |
|
T130 |
4 |
|
T255 |
1 |
| others[1] |
102 |
1 |
|
T5 |
1 |
|
T43 |
3 |
|
T130 |
4 |
| others[2] |
109 |
1 |
|
T43 |
3 |
|
T130 |
5 |
|
T213 |
2 |
| others[3] |
161 |
1 |
|
T43 |
7 |
|
T130 |
3 |
|
T214 |
1 |
| false |
61 |
1 |
|
T5 |
1 |
|
T43 |
3 |
|
T130 |
4 |
| true |
6144 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T43 |
11 |
|
T130 |
7 |
|
T33 |
1 |
| others[1] |
217 |
1 |
|
T2 |
1 |
|
T43 |
10 |
|
T130 |
9 |
| others[2] |
220 |
1 |
|
T43 |
8 |
|
T130 |
9 |
|
T213 |
1 |
| others[3] |
383 |
1 |
|
T5 |
1 |
|
T43 |
16 |
|
T130 |
15 |
| false |
117 |
1 |
|
T43 |
7 |
|
T130 |
10 |
|
T47 |
1 |
| true |
5502 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1058 |
1 |
|
T3 |
5 |
|
T5 |
2 |
|
T10 |
17 |
| others[1] |
1077 |
1 |
|
T3 |
9 |
|
T10 |
18 |
|
T42 |
3 |
| others[2] |
1032 |
1 |
|
T3 |
4 |
|
T4 |
1 |
|
T10 |
17 |
| others[3] |
1673 |
1 |
|
T2 |
1 |
|
T3 |
8 |
|
T10 |
24 |
| false |
540 |
1 |
|
T3 |
2 |
|
T10 |
5 |
|
T42 |
2 |
| true |
1305 |
1 |
|
T3 |
34 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T43 |
10 |
|
T130 |
7 |
|
T14 |
1 |
| others[1] |
211 |
1 |
|
T6 |
1 |
|
T43 |
5 |
|
T130 |
9 |
| others[2] |
220 |
1 |
|
T16 |
1 |
|
T43 |
11 |
|
T130 |
11 |
| others[3] |
395 |
1 |
|
T43 |
26 |
|
T130 |
12 |
|
T50 |
1 |
| false |
131 |
1 |
|
T43 |
4 |
|
T130 |
9 |
|
T213 |
1 |
| true |
5507 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T43 |
13 |
|
T130 |
7 |
|
T33 |
1 |
| others[1] |
215 |
1 |
|
T5 |
1 |
|
T43 |
9 |
|
T130 |
12 |
| others[2] |
219 |
1 |
|
T43 |
7 |
|
T130 |
7 |
|
T131 |
1 |
| others[3] |
348 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T43 |
21 |
| false |
108 |
1 |
|
T43 |
2 |
|
T130 |
11 |
|
T391 |
1 |
| true |
5585 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1199 |
1 |
|
T3 |
12 |
|
T10 |
17 |
|
T43 |
13 |
| others[1] |
1212 |
1 |
|
T3 |
10 |
|
T10 |
11 |
|
T42 |
2 |
| others[2] |
1244 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T5 |
1 |
| others[3] |
2086 |
1 |
|
T3 |
26 |
|
T5 |
1 |
|
T10 |
36 |
| false |
632 |
1 |
|
T3 |
7 |
|
T10 |
5 |
|
T26 |
1 |
| true |
312 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1193 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T10 |
10 |
| others[1] |
1268 |
1 |
|
T3 |
13 |
|
T10 |
20 |
|
T42 |
2 |
| others[2] |
1236 |
1 |
|
T3 |
7 |
|
T10 |
18 |
|
T26 |
1 |
| others[3] |
2013 |
1 |
|
T3 |
22 |
|
T5 |
2 |
|
T10 |
23 |
| false |
686 |
1 |
|
T3 |
7 |
|
T10 |
10 |
|
T42 |
1 |
| true |
289 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T5 |
1 |
|
T43 |
6 |
|
T130 |
6 |
| others[1] |
98 |
1 |
|
T5 |
1 |
|
T43 |
6 |
|
T130 |
6 |
| others[2] |
116 |
1 |
|
T43 |
5 |
|
T130 |
4 |
|
T213 |
1 |
| others[3] |
178 |
1 |
|
T43 |
6 |
|
T130 |
8 |
|
T255 |
1 |
| false |
48 |
1 |
|
T43 |
4 |
|
T130 |
2 |
|
T213 |
1 |
| true |
6143 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T17 |
1 |
|
T43 |
16 |
|
T130 |
9 |
| others[1] |
241 |
1 |
|
T43 |
11 |
|
T130 |
9 |
|
T13 |
1 |
| others[2] |
213 |
1 |
|
T43 |
10 |
|
T130 |
11 |
|
T131 |
1 |
| others[3] |
394 |
1 |
|
T5 |
1 |
|
T43 |
16 |
|
T130 |
17 |
| false |
117 |
1 |
|
T6 |
1 |
|
T43 |
7 |
|
T130 |
9 |
| true |
5512 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1009 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T5 |
1 |
| others[1] |
1033 |
1 |
|
T3 |
5 |
|
T10 |
18 |
|
T42 |
5 |
| others[2] |
1060 |
1 |
|
T3 |
8 |
|
T5 |
1 |
|
T6 |
1 |
| others[3] |
1710 |
1 |
|
T3 |
13 |
|
T10 |
24 |
|
T42 |
4 |
| false |
557 |
1 |
|
T3 |
3 |
|
T10 |
14 |
|
T42 |
2 |
| true |
1316 |
1 |
|
T3 |
26 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T5 |
2 |
|
T43 |
12 |
|
T130 |
9 |
| others[1] |
217 |
1 |
|
T43 |
8 |
|
T130 |
7 |
|
T90 |
1 |
| others[2] |
214 |
1 |
|
T43 |
9 |
|
T130 |
8 |
|
T33 |
1 |
| others[3] |
373 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T43 |
20 |
| false |
115 |
1 |
|
T43 |
3 |
|
T130 |
3 |
|
T214 |
1 |
| true |
5565 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T43 |
17 |
|
T130 |
6 |
|
T133 |
13 |
| others[1] |
216 |
1 |
|
T43 |
9 |
|
T130 |
12 |
|
T33 |
1 |
| others[2] |
239 |
1 |
|
T43 |
11 |
|
T130 |
8 |
|
T390 |
1 |
| others[3] |
343 |
1 |
|
T43 |
13 |
|
T130 |
20 |
|
T133 |
14 |
| false |
129 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
| true |
5535 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1200 |
1 |
|
T3 |
12 |
|
T10 |
21 |
|
T26 |
1 |
| others[1] |
1228 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T5 |
1 |
| others[2] |
1236 |
1 |
|
T3 |
11 |
|
T10 |
11 |
|
T42 |
2 |
| others[3] |
2027 |
1 |
|
T3 |
18 |
|
T5 |
1 |
|
T10 |
28 |
| false |
669 |
1 |
|
T3 |
8 |
|
T10 |
6 |
|
T43 |
10 |
| true |
325 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T42 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T3 |
11 |
|
T10 |
21 |
|
T7 |
1 |
| others[1] |
1200 |
1 |
|
T3 |
16 |
|
T10 |
20 |
|
T42 |
5 |
| others[2] |
1246 |
1 |
|
T3 |
7 |
|
T5 |
2 |
|
T10 |
15 |
| others[3] |
2089 |
1 |
|
T2 |
1 |
|
T3 |
23 |
|
T10 |
18 |
| false |
639 |
1 |
|
T3 |
5 |
|
T10 |
7 |
|
T42 |
1 |
| true |
284 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T43 |
6 |
|
T130 |
1 |
|
T92 |
1 |
| others[1] |
109 |
1 |
|
T43 |
4 |
|
T130 |
1 |
|
T213 |
1 |
| others[2] |
96 |
1 |
|
T5 |
2 |
|
T43 |
1 |
|
T130 |
2 |
| others[3] |
184 |
1 |
|
T43 |
6 |
|
T130 |
8 |
|
T50 |
1 |
| false |
48 |
1 |
|
T43 |
1 |
|
T130 |
3 |
|
T133 |
2 |
| true |
6140 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T6 |
1 |
|
T43 |
12 |
|
T130 |
15 |
| others[1] |
214 |
1 |
|
T5 |
1 |
|
T43 |
7 |
|
T130 |
8 |
| others[2] |
235 |
1 |
|
T17 |
1 |
|
T43 |
12 |
|
T130 |
8 |
| others[3] |
416 |
1 |
|
T5 |
1 |
|
T43 |
21 |
|
T130 |
19 |
| false |
126 |
1 |
|
T43 |
3 |
|
T130 |
7 |
|
T33 |
1 |
| true |
5463 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1020 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T10 |
19 |
| others[1] |
1021 |
1 |
|
T3 |
4 |
|
T10 |
18 |
|
T42 |
2 |
| others[2] |
1042 |
1 |
|
T3 |
5 |
|
T10 |
9 |
|
T42 |
4 |
| others[3] |
1702 |
1 |
|
T3 |
9 |
|
T5 |
1 |
|
T10 |
22 |
| false |
563 |
1 |
|
T3 |
3 |
|
T5 |
1 |
|
T10 |
13 |
| true |
1337 |
1 |
|
T3 |
36 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T43 |
10 |
| others[1] |
227 |
1 |
|
T2 |
1 |
|
T43 |
12 |
|
T130 |
8 |
| others[2] |
214 |
1 |
|
T43 |
9 |
|
T130 |
11 |
|
T133 |
11 |
| others[3] |
366 |
1 |
|
T5 |
1 |
|
T43 |
14 |
|
T130 |
18 |
| false |
107 |
1 |
|
T17 |
1 |
|
T43 |
4 |
|
T130 |
1 |
| true |
5538 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
190 |
1 |
|
T43 |
11 |
|
T130 |
8 |
|
T255 |
1 |
| others[1] |
232 |
1 |
|
T43 |
8 |
|
T130 |
7 |
|
T33 |
1 |
| others[2] |
200 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T43 |
8 |
| others[3] |
372 |
1 |
|
T17 |
1 |
|
T43 |
10 |
|
T130 |
22 |
| false |
124 |
1 |
|
T43 |
8 |
|
T130 |
2 |
|
T47 |
1 |
| true |
5567 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T3 |
14 |
|
T10 |
16 |
|
T42 |
1 |
| others[1] |
1198 |
1 |
|
T2 |
1 |
|
T3 |
12 |
|
T5 |
2 |
| others[2] |
1214 |
1 |
|
T3 |
10 |
|
T10 |
15 |
|
T26 |
1 |
| others[3] |
2083 |
1 |
|
T3 |
22 |
|
T10 |
21 |
|
T42 |
5 |
| false |
631 |
1 |
|
T3 |
4 |
|
T10 |
11 |
|
T388 |
1 |
| true |
323 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1242 |
1 |
|
T3 |
16 |
|
T5 |
1 |
|
T10 |
17 |
| others[1] |
1255 |
1 |
|
T3 |
10 |
|
T10 |
18 |
|
T42 |
3 |
| others[2] |
1215 |
1 |
|
T3 |
11 |
|
T10 |
17 |
|
T42 |
3 |
| others[3] |
2049 |
1 |
|
T2 |
1 |
|
T3 |
22 |
|
T10 |
22 |
| false |
632 |
1 |
|
T3 |
3 |
|
T5 |
1 |
|
T10 |
7 |
| true |
292 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T43 |
5 |
|
T130 |
5 |
|
T47 |
1 |
| others[1] |
111 |
1 |
|
T5 |
1 |
|
T43 |
1 |
|
T130 |
5 |
| others[2] |
116 |
1 |
|
T43 |
5 |
|
T130 |
4 |
|
T131 |
1 |
| others[3] |
173 |
1 |
|
T5 |
1 |
|
T43 |
5 |
|
T130 |
9 |
| false |
50 |
1 |
|
T43 |
3 |
|
T130 |
1 |
|
T214 |
1 |
| true |
6134 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T2 |
1 |
|
T43 |
14 |
|
T130 |
9 |
| others[1] |
213 |
1 |
|
T16 |
1 |
|
T43 |
9 |
|
T130 |
10 |
| others[2] |
207 |
1 |
|
T43 |
8 |
|
T130 |
9 |
|
T89 |
1 |
| others[3] |
400 |
1 |
|
T17 |
1 |
|
T43 |
18 |
|
T130 |
13 |
| false |
127 |
1 |
|
T43 |
4 |
|
T130 |
5 |
|
T132 |
1 |
| true |
5520 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1097 |
1 |
|
T3 |
5 |
|
T6 |
1 |
|
T10 |
22 |
| others[1] |
979 |
1 |
|
T3 |
5 |
|
T10 |
12 |
|
T42 |
3 |
| others[2] |
1048 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T10 |
15 |
| others[3] |
1707 |
1 |
|
T3 |
11 |
|
T5 |
2 |
|
T10 |
27 |
| false |
543 |
1 |
|
T3 |
1 |
|
T10 |
5 |
|
T42 |
1 |
| true |
1311 |
1 |
|
T3 |
35 |
|
T4 |
1 |
|
T26 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |