Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T43 |
5 |
|
T130 |
6 |
|
T13 |
1 |
| others[1] |
209 |
1 |
|
T5 |
1 |
|
T43 |
10 |
|
T130 |
10 |
| others[2] |
235 |
1 |
|
T2 |
1 |
|
T43 |
7 |
|
T130 |
11 |
| others[3] |
362 |
1 |
|
T43 |
17 |
|
T130 |
19 |
|
T213 |
1 |
| false |
131 |
1 |
|
T43 |
6 |
|
T130 |
4 |
|
T133 |
7 |
| true |
5532 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T43 |
8 |
| others[1] |
200 |
1 |
|
T2 |
1 |
|
T43 |
8 |
|
T130 |
7 |
| others[2] |
209 |
1 |
|
T43 |
11 |
|
T130 |
7 |
|
T33 |
1 |
| others[3] |
370 |
1 |
|
T5 |
1 |
|
T43 |
21 |
|
T130 |
19 |
| false |
112 |
1 |
|
T43 |
7 |
|
T130 |
7 |
|
T133 |
4 |
| true |
5593 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T3 |
13 |
|
T5 |
1 |
|
T10 |
17 |
| others[1] |
1195 |
1 |
|
T3 |
9 |
|
T10 |
17 |
|
T43 |
18 |
| others[2] |
1196 |
1 |
|
T2 |
1 |
|
T3 |
9 |
|
T10 |
14 |
| others[3] |
2050 |
1 |
|
T3 |
24 |
|
T5 |
1 |
|
T10 |
22 |
| false |
686 |
1 |
|
T3 |
7 |
|
T10 |
11 |
|
T26 |
1 |
| true |
321 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T3 |
12 |
|
T10 |
13 |
|
T26 |
1 |
| others[1] |
1250 |
1 |
|
T3 |
10 |
|
T5 |
2 |
|
T10 |
16 |
| others[2] |
1274 |
1 |
|
T3 |
15 |
|
T10 |
18 |
|
T42 |
2 |
| others[3] |
1962 |
1 |
|
T2 |
1 |
|
T3 |
19 |
|
T10 |
25 |
| false |
658 |
1 |
|
T3 |
6 |
|
T10 |
9 |
|
T42 |
1 |
| true |
293 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T5 |
1 |
|
T43 |
3 |
|
T130 |
5 |
| others[1] |
85 |
1 |
|
T43 |
1 |
|
T130 |
3 |
|
T133 |
2 |
| others[2] |
124 |
1 |
|
T43 |
5 |
|
T130 |
6 |
|
T213 |
2 |
| others[3] |
160 |
1 |
|
T5 |
1 |
|
T43 |
8 |
|
T130 |
4 |
| false |
42 |
1 |
|
T43 |
2 |
|
T130 |
2 |
|
T255 |
1 |
| true |
6172 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T17 |
1 |
|
T43 |
12 |
|
T130 |
12 |
| others[1] |
204 |
1 |
|
T43 |
9 |
|
T130 |
7 |
|
T13 |
1 |
| others[2] |
200 |
1 |
|
T43 |
6 |
|
T130 |
7 |
|
T390 |
1 |
| others[3] |
387 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T16 |
1 |
| false |
118 |
1 |
|
T43 |
5 |
|
T130 |
6 |
|
T18 |
2 |
| true |
5558 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1036 |
1 |
|
T3 |
5 |
|
T10 |
15 |
|
T42 |
2 |
| others[1] |
1030 |
1 |
|
T3 |
7 |
|
T10 |
12 |
|
T42 |
5 |
| others[2] |
1000 |
1 |
|
T2 |
1 |
|
T3 |
4 |
|
T10 |
16 |
| others[3] |
1754 |
1 |
|
T3 |
13 |
|
T6 |
1 |
|
T10 |
31 |
| false |
542 |
1 |
|
T3 |
2 |
|
T5 |
2 |
|
T10 |
7 |
| true |
1323 |
1 |
|
T3 |
31 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T16 |
1 |
|
T43 |
7 |
|
T130 |
6 |
| others[1] |
225 |
1 |
|
T43 |
6 |
|
T130 |
10 |
|
T13 |
1 |
| others[2] |
218 |
1 |
|
T17 |
1 |
|
T43 |
11 |
|
T130 |
11 |
| others[3] |
379 |
1 |
|
T6 |
1 |
|
T43 |
24 |
|
T130 |
12 |
| false |
110 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T43 |
5 |
| true |
5540 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T43 |
5 |
|
T130 |
5 |
|
T214 |
1 |
| others[1] |
231 |
1 |
|
T5 |
1 |
|
T43 |
8 |
|
T130 |
10 |
| others[2] |
212 |
1 |
|
T2 |
1 |
|
T43 |
10 |
|
T130 |
9 |
| others[3] |
364 |
1 |
|
T6 |
1 |
|
T43 |
16 |
|
T130 |
21 |
| false |
107 |
1 |
|
T43 |
8 |
|
T130 |
4 |
|
T47 |
1 |
| true |
5562 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1224 |
1 |
|
T2 |
1 |
|
T3 |
8 |
|
T5 |
2 |
| others[1] |
1222 |
1 |
|
T3 |
11 |
|
T10 |
19 |
|
T42 |
3 |
| others[2] |
1251 |
1 |
|
T3 |
12 |
|
T10 |
10 |
|
T16 |
1 |
| others[3] |
2047 |
1 |
|
T3 |
27 |
|
T10 |
27 |
|
T42 |
2 |
| false |
612 |
1 |
|
T3 |
4 |
|
T10 |
9 |
|
T388 |
1 |
| true |
329 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T42 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1193 |
1 |
|
T3 |
7 |
|
T5 |
1 |
|
T10 |
10 |
| others[1] |
1250 |
1 |
|
T2 |
1 |
|
T3 |
21 |
|
T5 |
1 |
| others[2] |
1192 |
1 |
|
T3 |
7 |
|
T10 |
15 |
|
T42 |
5 |
| others[3] |
2095 |
1 |
|
T3 |
19 |
|
T10 |
26 |
|
T42 |
6 |
| false |
655 |
1 |
|
T3 |
8 |
|
T6 |
1 |
|
T10 |
11 |
| true |
300 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T43 |
3 |
|
T130 |
9 |
|
T132 |
1 |
| others[1] |
102 |
1 |
|
T43 |
6 |
|
T130 |
5 |
|
T214 |
1 |
| others[2] |
98 |
1 |
|
T5 |
1 |
|
T43 |
3 |
|
T130 |
3 |
| others[3] |
189 |
1 |
|
T5 |
1 |
|
T43 |
5 |
|
T130 |
9 |
| false |
43 |
1 |
|
T43 |
2 |
|
T130 |
2 |
|
T133 |
4 |
| true |
6138 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T43 |
8 |
| others[1] |
224 |
1 |
|
T16 |
1 |
|
T43 |
3 |
|
T130 |
8 |
| others[2] |
245 |
1 |
|
T43 |
15 |
|
T130 |
8 |
|
T13 |
1 |
| others[3] |
387 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T43 |
18 |
| false |
111 |
1 |
|
T43 |
3 |
|
T130 |
11 |
|
T133 |
9 |
| true |
5485 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1058 |
1 |
|
T3 |
4 |
|
T5 |
1 |
|
T10 |
17 |
| others[1] |
1071 |
1 |
|
T3 |
6 |
|
T10 |
15 |
|
T42 |
3 |
| others[2] |
1003 |
1 |
|
T2 |
1 |
|
T3 |
8 |
|
T10 |
19 |
| others[3] |
1709 |
1 |
|
T3 |
7 |
|
T4 |
1 |
|
T5 |
1 |
| false |
499 |
1 |
|
T3 |
4 |
|
T10 |
1 |
|
T42 |
2 |
| true |
1345 |
1 |
|
T3 |
33 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T43 |
10 |
|
T130 |
9 |
|
T89 |
1 |
| others[1] |
222 |
1 |
|
T43 |
14 |
|
T130 |
4 |
|
T13 |
1 |
| others[2] |
212 |
1 |
|
T43 |
10 |
|
T130 |
9 |
|
T129 |
1 |
| others[3] |
360 |
1 |
|
T43 |
11 |
|
T130 |
21 |
|
T131 |
1 |
| false |
125 |
1 |
|
T43 |
10 |
|
T130 |
2 |
|
T92 |
1 |
| true |
5533 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T43 |
8 |
|
T130 |
9 |
|
T131 |
1 |
| others[1] |
214 |
1 |
|
T43 |
9 |
|
T130 |
8 |
|
T47 |
1 |
| others[2] |
227 |
1 |
|
T5 |
1 |
|
T43 |
11 |
|
T130 |
17 |
| others[3] |
328 |
1 |
|
T43 |
10 |
|
T130 |
13 |
|
T390 |
1 |
| false |
123 |
1 |
|
T43 |
4 |
|
T130 |
9 |
|
T133 |
7 |
| true |
5580 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1217 |
1 |
|
T3 |
15 |
|
T5 |
1 |
|
T10 |
19 |
| others[1] |
1223 |
1 |
|
T2 |
1 |
|
T3 |
15 |
|
T10 |
15 |
| others[2] |
1210 |
1 |
|
T3 |
6 |
|
T10 |
18 |
|
T26 |
1 |
| others[3] |
2059 |
1 |
|
T3 |
21 |
|
T10 |
23 |
|
T42 |
2 |
| false |
642 |
1 |
|
T3 |
5 |
|
T5 |
1 |
|
T10 |
6 |
| true |
334 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T3 |
10 |
|
T10 |
14 |
|
T42 |
2 |
| others[1] |
1264 |
1 |
|
T3 |
13 |
|
T10 |
10 |
|
T42 |
4 |
| others[2] |
1225 |
1 |
|
T3 |
12 |
|
T5 |
2 |
|
T10 |
29 |
| others[3] |
2033 |
1 |
|
T2 |
1 |
|
T3 |
19 |
|
T10 |
21 |
| false |
651 |
1 |
|
T3 |
8 |
|
T10 |
7 |
|
T43 |
11 |
| true |
299 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T5 |
1 |
|
T43 |
7 |
|
T130 |
3 |
| others[1] |
115 |
1 |
|
T5 |
1 |
|
T43 |
1 |
|
T130 |
3 |
| others[2] |
88 |
1 |
|
T16 |
1 |
|
T43 |
4 |
|
T130 |
3 |
| others[3] |
162 |
1 |
|
T43 |
5 |
|
T130 |
8 |
|
T255 |
1 |
| false |
67 |
1 |
|
T43 |
2 |
|
T130 |
2 |
|
T214 |
1 |
| true |
6151 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T43 |
10 |
|
T130 |
4 |
|
T213 |
1 |
| others[1] |
196 |
1 |
|
T6 |
1 |
|
T43 |
8 |
|
T130 |
8 |
| others[2] |
229 |
1 |
|
T5 |
1 |
|
T43 |
8 |
|
T130 |
15 |
| others[3] |
407 |
1 |
|
T5 |
1 |
|
T43 |
20 |
|
T130 |
17 |
| false |
112 |
1 |
|
T16 |
1 |
|
T43 |
5 |
|
T130 |
7 |
| true |
5543 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1026 |
1 |
|
T3 |
7 |
|
T6 |
1 |
|
T10 |
15 |
| others[1] |
1047 |
1 |
|
T3 |
7 |
|
T4 |
1 |
|
T5 |
2 |
| others[2] |
1015 |
1 |
|
T3 |
5 |
|
T10 |
15 |
|
T42 |
5 |
| others[3] |
1746 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T10 |
20 |
| false |
538 |
1 |
|
T3 |
3 |
|
T10 |
12 |
|
T42 |
2 |
| true |
1313 |
1 |
|
T3 |
35 |
|
T102 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T5 |
1 |
|
T43 |
17 |
|
T130 |
9 |
| others[1] |
255 |
1 |
|
T2 |
1 |
|
T43 |
11 |
|
T130 |
8 |
| others[2] |
217 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T43 |
5 |
| others[3] |
372 |
1 |
|
T43 |
19 |
|
T130 |
16 |
|
T33 |
1 |
| false |
116 |
1 |
|
T43 |
2 |
|
T130 |
3 |
|
T13 |
1 |
| true |
5501 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T5 |
1 |
|
T43 |
5 |
|
T130 |
8 |
| others[1] |
225 |
1 |
|
T5 |
1 |
|
T43 |
12 |
|
T130 |
10 |
| others[2] |
229 |
1 |
|
T6 |
1 |
|
T43 |
9 |
|
T130 |
7 |
| others[3] |
338 |
1 |
|
T43 |
14 |
|
T130 |
17 |
|
T255 |
1 |
| false |
135 |
1 |
|
T43 |
7 |
|
T130 |
3 |
|
T390 |
1 |
| true |
5534 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T2 |
1 |
|
T3 |
9 |
|
T5 |
1 |
| others[1] |
1244 |
1 |
|
T3 |
11 |
|
T10 |
18 |
|
T42 |
1 |
| others[2] |
1172 |
1 |
|
T3 |
10 |
|
T5 |
1 |
|
T10 |
13 |
| others[3] |
2093 |
1 |
|
T3 |
24 |
|
T10 |
26 |
|
T42 |
2 |
| false |
623 |
1 |
|
T3 |
8 |
|
T10 |
12 |
|
T26 |
1 |
| true |
333 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T3 |
11 |
|
T5 |
1 |
|
T10 |
17 |
| others[1] |
1201 |
1 |
|
T3 |
8 |
|
T10 |
17 |
|
T42 |
3 |
| others[2] |
1240 |
1 |
|
T3 |
13 |
|
T5 |
1 |
|
T10 |
17 |
| others[3] |
2059 |
1 |
|
T2 |
1 |
|
T3 |
24 |
|
T10 |
21 |
| false |
618 |
1 |
|
T3 |
6 |
|
T10 |
9 |
|
T42 |
1 |
| true |
294 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T6 |
1 |
|
T43 |
4 |
|
T130 |
3 |
| others[1] |
104 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T43 |
4 |
| others[2] |
91 |
1 |
|
T43 |
6 |
|
T130 |
4 |
|
T131 |
1 |
| others[3] |
177 |
1 |
|
T5 |
1 |
|
T43 |
7 |
|
T130 |
6 |
| false |
55 |
1 |
|
T43 |
1 |
|
T213 |
1 |
|
T133 |
1 |
| true |
6145 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T5 |
1 |
|
T43 |
8 |
|
T130 |
11 |
| others[1] |
230 |
1 |
|
T6 |
1 |
|
T43 |
13 |
|
T130 |
5 |
| others[2] |
248 |
1 |
|
T43 |
9 |
|
T11 |
1 |
|
T130 |
12 |
| others[3] |
363 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T43 |
19 |
| false |
109 |
1 |
|
T43 |
4 |
|
T130 |
5 |
|
T89 |
1 |
| true |
5513 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1016 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T10 |
13 |
| others[1] |
1021 |
1 |
|
T3 |
5 |
|
T10 |
24 |
|
T42 |
2 |
| others[2] |
1039 |
1 |
|
T3 |
6 |
|
T10 |
21 |
|
T42 |
3 |
| others[3] |
1718 |
1 |
|
T3 |
17 |
|
T5 |
1 |
|
T10 |
21 |
| false |
549 |
1 |
|
T3 |
3 |
|
T5 |
1 |
|
T10 |
2 |
| true |
1342 |
1 |
|
T3 |
24 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T6 |
1 |
|
T43 |
12 |
|
T130 |
7 |
| others[1] |
236 |
1 |
|
T5 |
1 |
|
T43 |
4 |
|
T130 |
11 |
| others[2] |
223 |
1 |
|
T43 |
12 |
|
T130 |
9 |
|
T92 |
1 |
| others[3] |
363 |
1 |
|
T5 |
1 |
|
T43 |
14 |
|
T130 |
21 |
| false |
112 |
1 |
|
T43 |
5 |
|
T130 |
2 |
|
T192 |
1 |
| true |
5515 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T5 |
1 |
|
T43 |
8 |
|
T130 |
10 |
| others[1] |
215 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T43 |
7 |
| others[2] |
207 |
1 |
|
T43 |
4 |
|
T130 |
12 |
|
T89 |
1 |
| others[3] |
341 |
1 |
|
T43 |
24 |
|
T130 |
14 |
|
T129 |
1 |
| false |
117 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T43 |
1 |
| true |
5593 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1180 |
1 |
|
T3 |
7 |
|
T10 |
13 |
|
T42 |
1 |
| others[1] |
1231 |
1 |
|
T3 |
14 |
|
T10 |
13 |
|
T26 |
1 |
| others[2] |
1269 |
1 |
|
T3 |
17 |
|
T10 |
21 |
|
T42 |
1 |
| others[3] |
2037 |
1 |
|
T2 |
1 |
|
T3 |
17 |
|
T5 |
2 |
| false |
649 |
1 |
|
T3 |
7 |
|
T10 |
12 |
|
T8 |
1 |
| true |
319 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |