Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1201 |
1 |
|
T3 |
9 |
|
T10 |
16 |
|
T42 |
2 |
| others[1] |
1245 |
1 |
|
T3 |
17 |
|
T5 |
1 |
|
T10 |
18 |
| others[2] |
1215 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T10 |
14 |
| others[3] |
2054 |
1 |
|
T3 |
21 |
|
T5 |
1 |
|
T10 |
30 |
| false |
674 |
1 |
|
T3 |
2 |
|
T10 |
3 |
|
T42 |
2 |
| true |
296 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T43 |
7 |
|
T130 |
4 |
|
T255 |
1 |
| others[1] |
117 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T43 |
5 |
| others[2] |
97 |
1 |
|
T5 |
1 |
|
T43 |
5 |
|
T130 |
4 |
| others[3] |
156 |
1 |
|
T43 |
9 |
|
T130 |
4 |
|
T214 |
1 |
| false |
67 |
1 |
|
T43 |
3 |
|
T130 |
4 |
|
T213 |
1 |
| true |
6139 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T43 |
9 |
|
T130 |
10 |
|
T90 |
1 |
| others[1] |
249 |
1 |
|
T5 |
1 |
|
T43 |
5 |
|
T130 |
7 |
| others[2] |
228 |
1 |
|
T43 |
13 |
|
T130 |
5 |
|
T391 |
1 |
| others[3] |
368 |
1 |
|
T43 |
14 |
|
T130 |
21 |
|
T90 |
2 |
| false |
119 |
1 |
|
T43 |
8 |
|
T130 |
5 |
|
T132 |
1 |
| true |
5487 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
993 |
1 |
|
T3 |
9 |
|
T5 |
1 |
|
T10 |
19 |
| others[1] |
1032 |
1 |
|
T3 |
11 |
|
T10 |
14 |
|
T42 |
4 |
| others[2] |
1000 |
1 |
|
T3 |
9 |
|
T5 |
1 |
|
T10 |
17 |
| others[3] |
1812 |
1 |
|
T3 |
5 |
|
T10 |
27 |
|
T26 |
1 |
| false |
532 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T10 |
4 |
| true |
1316 |
1 |
|
T3 |
26 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T43 |
7 |
|
T130 |
7 |
|
T390 |
1 |
| others[1] |
216 |
1 |
|
T43 |
10 |
|
T130 |
14 |
|
T133 |
6 |
| others[2] |
238 |
1 |
|
T16 |
1 |
|
T43 |
11 |
|
T130 |
16 |
| others[3] |
363 |
1 |
|
T43 |
17 |
|
T130 |
16 |
|
T13 |
1 |
| false |
122 |
1 |
|
T6 |
1 |
|
T43 |
4 |
|
T130 |
6 |
| true |
5525 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T6 |
1 |
|
T43 |
11 |
|
T130 |
6 |
| others[1] |
209 |
1 |
|
T43 |
7 |
|
T130 |
9 |
|
T131 |
1 |
| others[2] |
233 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T43 |
12 |
| others[3] |
391 |
1 |
|
T5 |
1 |
|
T43 |
25 |
|
T130 |
13 |
| false |
110 |
1 |
|
T43 |
6 |
|
T130 |
5 |
|
T33 |
1 |
| true |
5534 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T3 |
15 |
|
T5 |
1 |
|
T10 |
18 |
| others[1] |
1204 |
1 |
|
T3 |
8 |
|
T5 |
1 |
|
T10 |
15 |
| others[2] |
1284 |
1 |
|
T2 |
1 |
|
T3 |
18 |
|
T10 |
14 |
| others[3] |
1966 |
1 |
|
T3 |
18 |
|
T10 |
30 |
|
T26 |
1 |
| false |
670 |
1 |
|
T3 |
3 |
|
T10 |
4 |
|
T43 |
6 |
| true |
335 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1217 |
1 |
|
T3 |
8 |
|
T5 |
1 |
|
T10 |
15 |
| others[1] |
1235 |
1 |
|
T3 |
14 |
|
T10 |
19 |
|
T26 |
1 |
| others[2] |
1257 |
1 |
|
T3 |
15 |
|
T10 |
18 |
|
T42 |
2 |
| others[3] |
2073 |
1 |
|
T2 |
1 |
|
T3 |
15 |
|
T5 |
1 |
| false |
611 |
1 |
|
T3 |
10 |
|
T10 |
3 |
|
T42 |
4 |
| true |
292 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T43 |
5 |
|
T130 |
5 |
|
T214 |
1 |
| others[1] |
98 |
1 |
|
T43 |
4 |
|
T130 |
7 |
|
T214 |
1 |
| others[2] |
111 |
1 |
|
T17 |
1 |
|
T43 |
6 |
|
T130 |
7 |
| others[3] |
176 |
1 |
|
T5 |
2 |
|
T43 |
3 |
|
T130 |
7 |
| false |
50 |
1 |
|
T43 |
1 |
|
T130 |
2 |
|
T390 |
1 |
| true |
6156 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T43 |
8 |
|
T11 |
1 |
|
T130 |
8 |
| others[1] |
231 |
1 |
|
T16 |
1 |
|
T43 |
9 |
|
T130 |
12 |
| others[2] |
220 |
1 |
|
T43 |
11 |
|
T130 |
11 |
|
T92 |
1 |
| others[3] |
352 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T17 |
1 |
| false |
117 |
1 |
|
T43 |
5 |
|
T130 |
4 |
|
T13 |
1 |
| true |
5530 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1088 |
1 |
|
T3 |
5 |
|
T10 |
19 |
|
T42 |
4 |
| others[1] |
1015 |
1 |
|
T2 |
1 |
|
T3 |
3 |
|
T10 |
12 |
| others[2] |
1002 |
1 |
|
T3 |
7 |
|
T10 |
12 |
|
T42 |
4 |
| others[3] |
1719 |
1 |
|
T3 |
13 |
|
T4 |
1 |
|
T5 |
2 |
| false |
522 |
1 |
|
T10 |
9 |
|
T7 |
1 |
|
T43 |
16 |
| true |
1339 |
1 |
|
T3 |
34 |
|
T6 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T43 |
13 |
|
T130 |
6 |
|
T13 |
1 |
| others[1] |
240 |
1 |
|
T43 |
11 |
|
T130 |
11 |
|
T34 |
1 |
| others[2] |
233 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T43 |
12 |
| others[3] |
367 |
1 |
|
T43 |
12 |
|
T130 |
15 |
|
T92 |
1 |
| false |
117 |
1 |
|
T5 |
1 |
|
T43 |
7 |
|
T130 |
3 |
| true |
5524 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T16 |
1 |
|
T43 |
7 |
|
T130 |
18 |
| others[1] |
223 |
1 |
|
T6 |
1 |
|
T43 |
11 |
|
T130 |
6 |
| others[2] |
223 |
1 |
|
T2 |
1 |
|
T43 |
7 |
|
T130 |
8 |
| others[3] |
375 |
1 |
|
T5 |
2 |
|
T17 |
1 |
|
T43 |
16 |
| false |
116 |
1 |
|
T43 |
5 |
|
T130 |
6 |
|
T34 |
1 |
| true |
5537 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1276 |
1 |
|
T2 |
1 |
|
T3 |
10 |
|
T10 |
24 |
| others[1] |
1238 |
1 |
|
T3 |
9 |
|
T10 |
14 |
|
T16 |
1 |
| others[2] |
1161 |
1 |
|
T3 |
13 |
|
T10 |
16 |
|
T42 |
1 |
| others[3] |
2045 |
1 |
|
T3 |
24 |
|
T5 |
2 |
|
T10 |
19 |
| false |
636 |
1 |
|
T3 |
6 |
|
T10 |
8 |
|
T43 |
6 |
| true |
329 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T42 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1224 |
1 |
|
T3 |
13 |
|
T5 |
1 |
|
T10 |
18 |
| others[1] |
1229 |
1 |
|
T3 |
16 |
|
T5 |
1 |
|
T10 |
12 |
| others[2] |
1243 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T10 |
17 |
| others[3] |
2073 |
1 |
|
T3 |
15 |
|
T10 |
25 |
|
T42 |
7 |
| false |
618 |
1 |
|
T3 |
5 |
|
T10 |
9 |
|
T42 |
1 |
| true |
298 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T5 |
1 |
|
T43 |
2 |
|
T130 |
2 |
| others[1] |
106 |
1 |
|
T43 |
3 |
|
T130 |
4 |
|
T133 |
5 |
| others[2] |
104 |
1 |
|
T2 |
1 |
|
T43 |
5 |
|
T130 |
4 |
| others[3] |
187 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T43 |
9 |
| false |
58 |
1 |
|
T43 |
1 |
|
T130 |
1 |
|
T92 |
1 |
| true |
6124 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T43 |
6 |
|
T130 |
8 |
|
T132 |
1 |
| others[1] |
219 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T43 |
8 |
| others[2] |
226 |
1 |
|
T43 |
9 |
|
T130 |
12 |
|
T18 |
1 |
| others[3] |
362 |
1 |
|
T16 |
1 |
|
T43 |
14 |
|
T130 |
20 |
| false |
114 |
1 |
|
T43 |
3 |
|
T130 |
5 |
|
T18 |
3 |
| true |
5519 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1018 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T5 |
1 |
| others[1] |
1027 |
1 |
|
T3 |
4 |
|
T10 |
10 |
|
T42 |
1 |
| others[2] |
1017 |
1 |
|
T3 |
3 |
|
T10 |
18 |
|
T42 |
2 |
| others[3] |
1779 |
1 |
|
T3 |
11 |
|
T4 |
1 |
|
T5 |
1 |
| false |
526 |
1 |
|
T3 |
5 |
|
T10 |
8 |
|
T43 |
15 |
| true |
1318 |
1 |
|
T3 |
34 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T43 |
8 |
|
T130 |
12 |
|
T34 |
1 |
| others[1] |
205 |
1 |
|
T5 |
1 |
|
T43 |
4 |
|
T130 |
10 |
| others[2] |
208 |
1 |
|
T2 |
1 |
|
T43 |
18 |
|
T130 |
12 |
| others[3] |
403 |
1 |
|
T6 |
1 |
|
T43 |
14 |
|
T130 |
13 |
| false |
114 |
1 |
|
T43 |
3 |
|
T130 |
6 |
|
T13 |
1 |
| true |
5516 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T43 |
5 |
|
T130 |
8 |
|
T34 |
1 |
| others[1] |
211 |
1 |
|
T43 |
12 |
|
T130 |
11 |
|
T18 |
1 |
| others[2] |
213 |
1 |
|
T43 |
9 |
|
T130 |
9 |
|
T133 |
6 |
| others[3] |
394 |
1 |
|
T2 |
1 |
|
T43 |
16 |
|
T130 |
17 |
| false |
124 |
1 |
|
T6 |
1 |
|
T43 |
6 |
|
T130 |
7 |
| true |
5528 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T10 |
13 |
| others[1] |
1195 |
1 |
|
T3 |
10 |
|
T5 |
1 |
|
T10 |
19 |
| others[2] |
1211 |
1 |
|
T3 |
16 |
|
T10 |
15 |
|
T26 |
1 |
| others[3] |
2067 |
1 |
|
T3 |
16 |
|
T5 |
1 |
|
T10 |
27 |
| false |
645 |
1 |
|
T3 |
7 |
|
T10 |
7 |
|
T43 |
14 |
| true |
328 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1270 |
1 |
|
T3 |
14 |
|
T5 |
1 |
|
T10 |
15 |
| others[1] |
1246 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T10 |
22 |
| others[2] |
1247 |
1 |
|
T3 |
10 |
|
T10 |
21 |
|
T42 |
4 |
| others[3] |
1984 |
1 |
|
T3 |
18 |
|
T10 |
17 |
|
T26 |
1 |
| false |
643 |
1 |
|
T3 |
7 |
|
T5 |
1 |
|
T10 |
6 |
| true |
295 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T43 |
3 |
|
T133 |
3 |
|
T215 |
2 |
| others[1] |
105 |
1 |
|
T5 |
1 |
|
T43 |
5 |
|
T130 |
1 |
| others[2] |
108 |
1 |
|
T2 |
1 |
|
T43 |
7 |
|
T130 |
7 |
| others[3] |
183 |
1 |
|
T5 |
1 |
|
T43 |
10 |
|
T130 |
14 |
| false |
48 |
1 |
|
T43 |
2 |
|
T130 |
3 |
|
T129 |
1 |
| true |
6143 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T16 |
1 |
|
T43 |
8 |
|
T130 |
11 |
| others[1] |
229 |
1 |
|
T5 |
1 |
|
T43 |
10 |
|
T130 |
9 |
| others[2] |
226 |
1 |
|
T6 |
1 |
|
T43 |
10 |
|
T130 |
5 |
| others[3] |
335 |
1 |
|
T17 |
1 |
|
T43 |
14 |
|
T130 |
18 |
| false |
116 |
1 |
|
T5 |
1 |
|
T43 |
8 |
|
T11 |
1 |
| true |
5531 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1025 |
1 |
|
T3 |
6 |
|
T10 |
12 |
|
T42 |
2 |
| others[1] |
1042 |
1 |
|
T3 |
10 |
|
T5 |
1 |
|
T10 |
16 |
| others[2] |
1083 |
1 |
|
T2 |
1 |
|
T3 |
4 |
|
T5 |
1 |
| others[3] |
1741 |
1 |
|
T3 |
8 |
|
T10 |
28 |
|
T42 |
5 |
| false |
534 |
1 |
|
T3 |
3 |
|
T10 |
7 |
|
T42 |
2 |
| true |
1260 |
1 |
|
T3 |
31 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T43 |
11 |
|
T130 |
8 |
|
T89 |
1 |
| others[1] |
222 |
1 |
|
T16 |
1 |
|
T43 |
6 |
|
T130 |
11 |
| others[2] |
223 |
1 |
|
T43 |
8 |
|
T130 |
9 |
|
T146 |
1 |
| others[3] |
381 |
1 |
|
T17 |
1 |
|
T43 |
15 |
|
T130 |
15 |
| false |
109 |
1 |
|
T43 |
7 |
|
T130 |
7 |
|
T50 |
1 |
| true |
5513 |
1 |
|
T2 |
1 |
|
T3 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T43 |
11 |
|
T130 |
8 |
|
T214 |
1 |
| others[1] |
216 |
1 |
|
T16 |
1 |
|
T43 |
10 |
|
T130 |
11 |
| others[2] |
215 |
1 |
|
T43 |
6 |
|
T130 |
7 |
|
T133 |
11 |
| others[3] |
369 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T43 |
17 |
| false |
125 |
1 |
|
T43 |
8 |
|
T130 |
6 |
|
T133 |
2 |
| true |
5514 |
1 |
|
T3 |
62 |
|
T4 |
1 |
|
T5 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1272 |
1 |
|
T3 |
20 |
|
T5 |
1 |
|
T10 |
20 |
| others[1] |
1184 |
1 |
|
T2 |
1 |
|
T3 |
8 |
|
T5 |
1 |
| others[2] |
1208 |
1 |
|
T3 |
11 |
|
T10 |
14 |
|
T42 |
1 |
| others[3] |
2072 |
1 |
|
T3 |
18 |
|
T10 |
26 |
|
T42 |
5 |
| false |
631 |
1 |
|
T3 |
5 |
|
T6 |
1 |
|
T10 |
6 |
| true |
318 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T42 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T393 |
1 |
|
T394 |
1 |
|
T395 |
1 |
| others[1] |
6 |
1 |
|
T396 |
1 |
|
T397 |
1 |
|
T398 |
1 |
| others[2] |
9 |
1 |
|
T79 |
1 |
|
T39 |
1 |
|
T40 |
1 |
| others[3] |
10 |
1 |
|
T21 |
1 |
|
T107 |
1 |
|
T74 |
1 |
| false |
4 |
1 |
|
T399 |
1 |
|
T256 |
1 |
|
T400 |
1 |
| true |
39 |
1 |
|
T79 |
1 |
|
T75 |
2 |
|
T107 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T401 |
1 |
|
T402 |
1 |
|
T403 |
1 |
| others[1] |
5 |
1 |
|
T63 |
1 |
|
T404 |
1 |
|
T182 |
1 |
| others[2] |
2 |
1 |
|
T405 |
1 |
|
T406 |
1 |
|
- |
- |
| others[3] |
5 |
1 |
|
T49 |
1 |
|
T407 |
1 |
|
T408 |
1 |
| false |
7 |
1 |
|
T73 |
1 |
|
T409 |
1 |
|
T410 |
1 |
| true |
22 |
1 |
|
T88 |
1 |
|
T269 |
1 |
|
T314 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T401 |
1 |
|
T404 |
1 |
|
T411 |
1 |
| others[1] |
2 |
1 |
|
T63 |
1 |
|
T405 |
1 |
|
- |
- |
| others[2] |
2 |
1 |
|
T412 |
1 |
|
T182 |
1 |
|
- |
- |
| others[3] |
3 |
1 |
|
T73 |
1 |
|
T410 |
1 |
|
T402 |
1 |
| false |
12 |
1 |
|
T88 |
1 |
|
T413 |
1 |
|
T407 |
1 |
| true |
22 |
1 |
|
T49 |
1 |
|
T269 |
1 |
|
T314 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |