Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9346 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
62 |
| others[1] |
770 |
1 |
|
T10 |
10 |
|
T42 |
3 |
|
T8 |
1 |
| others[2] |
780 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T10 |
15 |
| others[3] |
1332 |
1 |
|
T10 |
30 |
|
T42 |
6 |
|
T64 |
2 |
| false |
408 |
1 |
|
T10 |
12 |
|
T43 |
9 |
|
T130 |
11 |
| true |
389 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2247 |
1 |
|
T3 |
13 |
|
T15 |
8 |
|
T10 |
12 |
| others[1] |
2258 |
1 |
|
T1 |
1 |
|
T3 |
14 |
|
T5 |
1 |
| others[2] |
2204 |
1 |
|
T1 |
1 |
|
T3 |
13 |
|
T15 |
8 |
| others[3] |
3693 |
1 |
|
T3 |
16 |
|
T5 |
1 |
|
T15 |
21 |
| false |
1122 |
1 |
|
T3 |
6 |
|
T15 |
1 |
|
T10 |
12 |
| true |
1501 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T42 |
15 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8790 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
261 |
1 |
|
T9 |
1 |
|
T64 |
4 |
|
T43 |
6 |
| others[2] |
266 |
1 |
|
T43 |
9 |
|
T130 |
9 |
|
T50 |
1 |
| others[3] |
409 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| false |
129 |
1 |
|
T64 |
1 |
|
T43 |
8 |
|
T130 |
3 |
| true |
3170 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8991 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T5 |
1 |
| others[1] |
437 |
1 |
|
T5 |
1 |
|
T10 |
8 |
|
T42 |
1 |
| others[2] |
456 |
1 |
|
T10 |
8 |
|
T42 |
1 |
|
T64 |
1 |
| others[3] |
762 |
1 |
|
T4 |
1 |
|
T10 |
14 |
|
T16 |
1 |
| false |
209 |
1 |
|
T10 |
4 |
|
T64 |
1 |
|
T43 |
4 |
| true |
2170 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T10 |
38 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8780 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
261 |
1 |
|
T43 |
10 |
|
T130 |
9 |
|
T132 |
1 |
| others[2] |
243 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T43 |
7 |
| others[3] |
419 |
1 |
|
T8 |
1 |
|
T9 |
1 |
|
T43 |
19 |
| false |
134 |
1 |
|
T43 |
5 |
|
T130 |
5 |
|
T133 |
7 |
| true |
3188 |
1 |
|
T4 |
1 |
|
T5 |
2 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8773 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
243 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T43 |
11 |
| others[2] |
242 |
1 |
|
T5 |
1 |
|
T43 |
8 |
|
T130 |
11 |
| others[3] |
415 |
1 |
|
T43 |
17 |
|
T130 |
22 |
|
T33 |
1 |
| false |
127 |
1 |
|
T43 |
6 |
|
T130 |
3 |
|
T265 |
1 |
| true |
3225 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9375 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
765 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
10 |
| others[2] |
824 |
1 |
|
T10 |
19 |
|
T42 |
4 |
|
T64 |
7 |
| others[3] |
1273 |
1 |
|
T5 |
1 |
|
T10 |
23 |
|
T42 |
5 |
| false |
403 |
1 |
|
T10 |
15 |
|
T42 |
1 |
|
T7 |
1 |
| true |
385 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9378 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
62 |
| others[1] |
767 |
1 |
|
T10 |
10 |
|
T42 |
5 |
|
T8 |
1 |
| others[2] |
816 |
1 |
|
T10 |
17 |
|
T42 |
3 |
|
T64 |
1 |
| others[3] |
1266 |
1 |
|
T10 |
29 |
|
T42 |
4 |
|
T7 |
1 |
| false |
364 |
1 |
|
T10 |
7 |
|
T42 |
1 |
|
T64 |
1 |
| true |
395 |
1 |
|
T4 |
1 |
|
T5 |
2 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2131 |
1 |
|
T3 |
8 |
|
T5 |
1 |
|
T15 |
7 |
| others[1] |
2263 |
1 |
|
T3 |
16 |
|
T15 |
7 |
|
T10 |
13 |
| others[2] |
2211 |
1 |
|
T3 |
10 |
|
T15 |
16 |
|
T6 |
1 |
| others[3] |
3707 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
14 |
| false |
1186 |
1 |
|
T3 |
14 |
|
T15 |
6 |
|
T10 |
17 |
| true |
1488 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T42 |
15 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8800 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T5 |
1 |
| others[1] |
284 |
1 |
|
T43 |
11 |
|
T130 |
8 |
|
T33 |
1 |
| others[2] |
281 |
1 |
|
T64 |
1 |
|
T43 |
14 |
|
T130 |
10 |
| others[3] |
416 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T64 |
4 |
| false |
131 |
1 |
|
T16 |
1 |
|
T388 |
1 |
|
T43 |
6 |
| true |
3074 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8986 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
475 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T10 |
9 |
| others[2] |
401 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
7 |
| others[3] |
727 |
1 |
|
T5 |
1 |
|
T10 |
17 |
|
T42 |
4 |
| false |
250 |
1 |
|
T10 |
6 |
|
T42 |
1 |
|
T9 |
1 |
| true |
2147 |
1 |
|
T10 |
35 |
|
T42 |
6 |
|
T64 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8790 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T5 |
1 |
| others[1] |
233 |
1 |
|
T388 |
1 |
|
T43 |
8 |
|
T130 |
9 |
| others[2] |
277 |
1 |
|
T9 |
1 |
|
T43 |
13 |
|
T130 |
6 |
| others[3] |
393 |
1 |
|
T16 |
1 |
|
T43 |
13 |
|
T130 |
17 |
| false |
140 |
1 |
|
T43 |
5 |
|
T130 |
5 |
|
T214 |
1 |
| true |
3153 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8761 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
264 |
1 |
|
T43 |
10 |
|
T130 |
9 |
|
T33 |
1 |
| others[2] |
250 |
1 |
|
T5 |
1 |
|
T43 |
11 |
|
T130 |
7 |
| others[3] |
416 |
1 |
|
T17 |
1 |
|
T43 |
20 |
|
T130 |
21 |
| false |
145 |
1 |
|
T388 |
1 |
|
T43 |
9 |
|
T130 |
5 |
| true |
3150 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9328 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T5 |
1 |
| others[1] |
752 |
1 |
|
T10 |
13 |
|
T42 |
2 |
|
T64 |
2 |
| others[2] |
780 |
1 |
|
T2 |
1 |
|
T10 |
12 |
|
T16 |
1 |
| others[3] |
1322 |
1 |
|
T10 |
25 |
|
T42 |
5 |
|
T9 |
1 |
| false |
409 |
1 |
|
T10 |
14 |
|
T42 |
1 |
|
T7 |
1 |
| true |
395 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9339 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T5 |
1 |
| others[1] |
752 |
1 |
|
T2 |
1 |
|
T10 |
16 |
|
T42 |
3 |
| others[2] |
767 |
1 |
|
T10 |
22 |
|
T42 |
4 |
|
T7 |
1 |
| others[3] |
1295 |
1 |
|
T10 |
24 |
|
T42 |
4 |
|
T8 |
1 |
| false |
430 |
1 |
|
T10 |
6 |
|
T42 |
3 |
|
T43 |
6 |
| true |
403 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2225 |
1 |
|
T1 |
1 |
|
T3 |
11 |
|
T15 |
8 |
| others[1] |
2216 |
1 |
|
T1 |
1 |
|
T3 |
6 |
|
T5 |
1 |
| others[2] |
2244 |
1 |
|
T2 |
1 |
|
T3 |
12 |
|
T5 |
1 |
| others[3] |
3622 |
1 |
|
T3 |
20 |
|
T15 |
14 |
|
T10 |
32 |
| false |
1172 |
1 |
|
T3 |
13 |
|
T15 |
7 |
|
T10 |
6 |
| true |
1507 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T42 |
15 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8795 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
62 |
| others[1] |
244 |
1 |
|
T8 |
1 |
|
T43 |
6 |
|
T130 |
12 |
| others[2] |
235 |
1 |
|
T5 |
1 |
|
T43 |
12 |
|
T130 |
10 |
| others[3] |
424 |
1 |
|
T16 |
1 |
|
T9 |
1 |
|
T64 |
3 |
| false |
132 |
1 |
|
T64 |
1 |
|
T43 |
7 |
|
T130 |
7 |
| true |
3156 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8972 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
462 |
1 |
|
T5 |
1 |
|
T10 |
7 |
|
T42 |
1 |
| others[2] |
442 |
1 |
|
T10 |
6 |
|
T64 |
1 |
|
T43 |
12 |
| others[3] |
728 |
1 |
|
T10 |
17 |
|
T42 |
4 |
|
T64 |
3 |
| false |
244 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T10 |
4 |
| true |
2138 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T10 |
44 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8782 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
252 |
1 |
|
T2 |
1 |
|
T388 |
1 |
|
T43 |
14 |
| others[2] |
260 |
1 |
|
T43 |
9 |
|
T130 |
12 |
|
T14 |
1 |
| others[3] |
426 |
1 |
|
T7 |
1 |
|
T17 |
1 |
|
T9 |
1 |
| false |
136 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T43 |
8 |
| true |
3130 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8782 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
272 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T43 |
7 |
| others[2] |
216 |
1 |
|
T16 |
1 |
|
T43 |
11 |
|
T130 |
15 |
| others[3] |
390 |
1 |
|
T6 |
1 |
|
T43 |
19 |
|
T130 |
12 |
| false |
122 |
1 |
|
T43 |
3 |
|
T130 |
2 |
|
T213 |
1 |
| true |
3204 |
1 |
|
T4 |
1 |
|
T5 |
2 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9296 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
793 |
1 |
|
T10 |
10 |
|
T42 |
7 |
|
T21 |
1 |
| others[2] |
814 |
1 |
|
T5 |
1 |
|
T10 |
21 |
|
T42 |
4 |
| others[3] |
1312 |
1 |
|
T2 |
1 |
|
T10 |
26 |
|
T42 |
1 |
| false |
390 |
1 |
|
T10 |
4 |
|
T42 |
1 |
|
T64 |
2 |
| true |
381 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9317 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
784 |
1 |
|
T2 |
1 |
|
T10 |
18 |
|
T42 |
2 |
| others[2] |
797 |
1 |
|
T10 |
12 |
|
T42 |
3 |
|
T7 |
1 |
| others[3] |
1272 |
1 |
|
T5 |
1 |
|
T10 |
25 |
|
T42 |
7 |
| false |
412 |
1 |
|
T5 |
1 |
|
T10 |
10 |
|
T42 |
2 |
| true |
404 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2272 |
1 |
|
T1 |
1 |
|
T3 |
13 |
|
T15 |
8 |
| others[1] |
2177 |
1 |
|
T1 |
1 |
|
T3 |
11 |
|
T15 |
15 |
| others[2] |
2191 |
1 |
|
T3 |
13 |
|
T15 |
6 |
|
T10 |
17 |
| others[3] |
3813 |
1 |
|
T3 |
23 |
|
T5 |
2 |
|
T15 |
15 |
| false |
1116 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T15 |
4 |
| true |
1417 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T42 |
15 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8794 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
228 |
1 |
|
T43 |
11 |
|
T130 |
11 |
|
T34 |
1 |
| others[2] |
256 |
1 |
|
T6 |
1 |
|
T43 |
8 |
|
T130 |
12 |
| others[3] |
461 |
1 |
|
T2 |
1 |
|
T64 |
1 |
|
T43 |
24 |
| false |
144 |
1 |
|
T64 |
2 |
|
T43 |
10 |
|
T130 |
6 |
| true |
3103 |
1 |
|
T4 |
1 |
|
T5 |
2 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8974 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
442 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
5 |
| others[2] |
479 |
1 |
|
T10 |
4 |
|
T64 |
2 |
|
T388 |
1 |
| others[3] |
760 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T10 |
13 |
| false |
246 |
1 |
|
T6 |
1 |
|
T42 |
1 |
|
T64 |
1 |
| true |
2085 |
1 |
|
T10 |
50 |
|
T16 |
1 |
|
T42 |
9 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8791 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
251 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T43 |
10 |
| others[2] |
228 |
1 |
|
T16 |
1 |
|
T43 |
5 |
|
T130 |
7 |
| others[3] |
431 |
1 |
|
T43 |
22 |
|
T130 |
10 |
|
T34 |
1 |
| false |
132 |
1 |
|
T43 |
3 |
|
T130 |
8 |
|
T33 |
1 |
| true |
3153 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8759 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
265 |
1 |
|
T5 |
1 |
|
T43 |
13 |
|
T130 |
11 |
| others[2] |
224 |
1 |
|
T43 |
11 |
|
T130 |
9 |
|
T389 |
1 |
| others[3] |
437 |
1 |
|
T5 |
1 |
|
T7 |
1 |
|
T17 |
1 |
| false |
150 |
1 |
|
T388 |
1 |
|
T43 |
2 |
|
T130 |
7 |
| true |
3151 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9333 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
774 |
1 |
|
T10 |
15 |
|
T42 |
3 |
|
T64 |
3 |
| others[2] |
755 |
1 |
|
T6 |
1 |
|
T10 |
17 |
|
T42 |
2 |
| others[3] |
1316 |
1 |
|
T10 |
25 |
|
T42 |
4 |
|
T7 |
1 |
| false |
397 |
1 |
|
T2 |
1 |
|
T10 |
5 |
|
T43 |
8 |
| true |
411 |
1 |
|
T4 |
1 |
|
T5 |
2 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9294 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
792 |
1 |
|
T10 |
18 |
|
T42 |
1 |
|
T9 |
1 |
| others[2] |
763 |
1 |
|
T10 |
15 |
|
T42 |
1 |
|
T64 |
2 |
| others[3] |
1374 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
27 |
| false |
375 |
1 |
|
T6 |
1 |
|
T10 |
5 |
|
T42 |
3 |
| true |
388 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2250 |
1 |
|
T3 |
17 |
|
T5 |
1 |
|
T15 |
9 |
| others[1] |
2246 |
1 |
|
T1 |
1 |
|
T3 |
10 |
|
T15 |
7 |
| others[2] |
2256 |
1 |
|
T3 |
13 |
|
T15 |
10 |
|
T10 |
13 |
| others[3] |
3609 |
1 |
|
T1 |
1 |
|
T3 |
19 |
|
T15 |
19 |
| false |
1167 |
1 |
|
T3 |
3 |
|
T5 |
1 |
|
T15 |
3 |
| true |
1458 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8791 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
251 |
1 |
|
T5 |
1 |
|
T388 |
1 |
|
T43 |
9 |
| others[2] |
266 |
1 |
|
T64 |
1 |
|
T43 |
12 |
|
T130 |
12 |
| others[3] |
429 |
1 |
|
T2 |
1 |
|
T64 |
3 |
|
T43 |
19 |
| false |
142 |
1 |
|
T43 |
5 |
|
T130 |
3 |
|
T12 |
1 |
| true |
3107 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |