Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8997 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
454 |
1 |
|
T10 |
12 |
|
T42 |
2 |
|
T9 |
1 |
| others[2] |
428 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
2 |
| others[3] |
714 |
1 |
|
T6 |
1 |
|
T10 |
14 |
|
T42 |
5 |
| false |
252 |
1 |
|
T5 |
1 |
|
T10 |
7 |
|
T64 |
1 |
| true |
2141 |
1 |
|
T4 |
1 |
|
T10 |
38 |
|
T42 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8797 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
249 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T43 |
9 |
| others[2] |
233 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T43 |
7 |
| others[3] |
413 |
1 |
|
T43 |
16 |
|
T130 |
19 |
|
T133 |
16 |
| false |
136 |
1 |
|
T2 |
1 |
|
T43 |
5 |
|
T130 |
5 |
| true |
3158 |
1 |
|
T4 |
1 |
|
T5 |
2 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8776 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
230 |
1 |
|
T5 |
1 |
|
T43 |
11 |
|
T130 |
9 |
| others[2] |
234 |
1 |
|
T9 |
1 |
|
T43 |
13 |
|
T130 |
9 |
| others[3] |
387 |
1 |
|
T2 |
1 |
|
T43 |
19 |
|
T130 |
11 |
| false |
107 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T43 |
3 |
| true |
3252 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9302 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
62 |
| others[1] |
756 |
1 |
|
T10 |
15 |
|
T42 |
2 |
|
T64 |
1 |
| others[2] |
803 |
1 |
|
T5 |
1 |
|
T10 |
15 |
|
T42 |
3 |
| others[3] |
1327 |
1 |
|
T10 |
24 |
|
T42 |
2 |
|
T21 |
1 |
| false |
417 |
1 |
|
T10 |
9 |
|
T42 |
3 |
|
T388 |
1 |
| true |
381 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9280 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
62 |
| others[1] |
784 |
1 |
|
T10 |
9 |
|
T42 |
1 |
|
T64 |
1 |
| others[2] |
798 |
1 |
|
T10 |
16 |
|
T42 |
6 |
|
T9 |
1 |
| others[3] |
1333 |
1 |
|
T10 |
31 |
|
T42 |
5 |
|
T7 |
1 |
| false |
399 |
1 |
|
T10 |
10 |
|
T42 |
1 |
|
T64 |
1 |
| true |
392 |
1 |
|
T4 |
1 |
|
T5 |
2 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2276 |
1 |
|
T3 |
14 |
|
T15 |
10 |
|
T10 |
17 |
| others[1] |
2280 |
1 |
|
T1 |
2 |
|
T3 |
7 |
|
T15 |
14 |
| others[2] |
2217 |
1 |
|
T3 |
11 |
|
T15 |
7 |
|
T10 |
17 |
| others[3] |
3632 |
1 |
|
T3 |
29 |
|
T5 |
1 |
|
T15 |
11 |
| false |
1120 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T15 |
6 |
| true |
1461 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T42 |
15 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8793 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
280 |
1 |
|
T5 |
1 |
|
T64 |
2 |
|
T43 |
10 |
| others[2] |
260 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T64 |
1 |
| others[3] |
404 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T17 |
1 |
| false |
140 |
1 |
|
T43 |
4 |
|
T130 |
5 |
|
T133 |
4 |
| true |
3109 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9000 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T4 |
1 |
| others[1] |
435 |
1 |
|
T10 |
7 |
|
T64 |
1 |
|
T102 |
1 |
| others[2] |
440 |
1 |
|
T5 |
1 |
|
T10 |
3 |
|
T42 |
2 |
| others[3] |
719 |
1 |
|
T6 |
1 |
|
T10 |
14 |
|
T42 |
3 |
| false |
240 |
1 |
|
T5 |
1 |
|
T10 |
3 |
|
T64 |
1 |
| true |
2152 |
1 |
|
T2 |
1 |
|
T10 |
45 |
|
T42 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8797 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T5 |
1 |
| others[1] |
229 |
1 |
|
T43 |
6 |
|
T130 |
6 |
|
T13 |
1 |
| others[2] |
246 |
1 |
|
T43 |
8 |
|
T130 |
12 |
|
T47 |
1 |
| others[3] |
387 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T43 |
18 |
| false |
138 |
1 |
|
T43 |
8 |
|
T130 |
3 |
|
T14 |
1 |
| true |
3189 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8792 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
225 |
1 |
|
T2 |
1 |
|
T43 |
7 |
|
T130 |
8 |
| others[2] |
245 |
1 |
|
T43 |
5 |
|
T130 |
7 |
|
T389 |
1 |
| others[3] |
397 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T388 |
1 |
| false |
127 |
1 |
|
T43 |
4 |
|
T130 |
7 |
|
T33 |
1 |
| true |
3200 |
1 |
|
T4 |
1 |
|
T5 |
2 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9348 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
759 |
1 |
|
T10 |
15 |
|
T42 |
3 |
|
T7 |
1 |
| others[2] |
756 |
1 |
|
T2 |
1 |
|
T10 |
15 |
|
T9 |
1 |
| others[3] |
1311 |
1 |
|
T5 |
2 |
|
T10 |
25 |
|
T16 |
1 |
| false |
428 |
1 |
|
T10 |
8 |
|
T64 |
1 |
|
T43 |
11 |
| true |
384 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9333 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
769 |
1 |
|
T10 |
12 |
|
T42 |
6 |
|
T64 |
2 |
| others[2] |
787 |
1 |
|
T2 |
1 |
|
T10 |
17 |
|
T42 |
2 |
| others[3] |
1326 |
1 |
|
T5 |
1 |
|
T10 |
30 |
|
T42 |
4 |
| false |
382 |
1 |
|
T10 |
7 |
|
T42 |
2 |
|
T64 |
2 |
| true |
389 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2234 |
1 |
|
T3 |
14 |
|
T5 |
1 |
|
T15 |
10 |
| others[1] |
2178 |
1 |
|
T1 |
1 |
|
T3 |
12 |
|
T15 |
6 |
| others[2] |
2243 |
1 |
|
T3 |
12 |
|
T5 |
1 |
|
T15 |
11 |
| others[3] |
3780 |
1 |
|
T3 |
18 |
|
T15 |
17 |
|
T10 |
20 |
| false |
1103 |
1 |
|
T1 |
1 |
|
T3 |
6 |
|
T15 |
4 |
| true |
1448 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8800 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
267 |
1 |
|
T64 |
2 |
|
T43 |
11 |
|
T130 |
7 |
| others[2] |
259 |
1 |
|
T64 |
1 |
|
T43 |
8 |
|
T11 |
1 |
| others[3] |
421 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T64 |
4 |
| false |
144 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T43 |
10 |
| true |
3095 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8992 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
462 |
1 |
|
T5 |
1 |
|
T10 |
8 |
|
T42 |
6 |
| others[2] |
424 |
1 |
|
T10 |
8 |
|
T42 |
1 |
|
T43 |
5 |
| others[3] |
743 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
10 |
| false |
249 |
1 |
|
T10 |
3 |
|
T42 |
1 |
|
T8 |
1 |
| true |
2116 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T10 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8792 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
246 |
1 |
|
T43 |
10 |
|
T130 |
6 |
|
T131 |
1 |
| others[2] |
245 |
1 |
|
T16 |
1 |
|
T43 |
16 |
|
T130 |
8 |
| others[3] |
435 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T43 |
19 |
| false |
129 |
1 |
|
T43 |
3 |
|
T130 |
6 |
|
T13 |
1 |
| true |
3139 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8784 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
237 |
1 |
|
T43 |
9 |
|
T130 |
10 |
|
T294 |
1 |
| others[2] |
248 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T43 |
2 |
| others[3] |
415 |
1 |
|
T43 |
27 |
|
T130 |
24 |
|
T33 |
1 |
| false |
122 |
1 |
|
T7 |
1 |
|
T43 |
5 |
|
T130 |
4 |
| true |
3180 |
1 |
|
T4 |
1 |
|
T5 |
2 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9344 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
62 |
| others[1] |
785 |
1 |
|
T10 |
24 |
|
T42 |
2 |
|
T64 |
2 |
| others[2] |
752 |
1 |
|
T10 |
15 |
|
T42 |
2 |
|
T64 |
4 |
| others[3] |
1290 |
1 |
|
T5 |
1 |
|
T10 |
25 |
|
T42 |
9 |
| false |
444 |
1 |
|
T10 |
10 |
|
T42 |
1 |
|
T7 |
1 |
| true |
371 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9317 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
831 |
1 |
|
T10 |
21 |
|
T42 |
1 |
|
T64 |
4 |
| others[2] |
771 |
1 |
|
T10 |
15 |
|
T42 |
3 |
|
T64 |
1 |
| others[3] |
1245 |
1 |
|
T2 |
1 |
|
T10 |
27 |
|
T42 |
10 |
| false |
415 |
1 |
|
T10 |
7 |
|
T42 |
1 |
|
T64 |
2 |
| true |
407 |
1 |
|
T4 |
1 |
|
T5 |
2 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2178 |
1 |
|
T3 |
12 |
|
T5 |
1 |
|
T15 |
9 |
| others[1] |
2240 |
1 |
|
T3 |
12 |
|
T5 |
1 |
|
T15 |
13 |
| others[2] |
2264 |
1 |
|
T3 |
8 |
|
T15 |
9 |
|
T10 |
18 |
| others[3] |
3646 |
1 |
|
T1 |
2 |
|
T3 |
20 |
|
T15 |
15 |
| false |
1191 |
1 |
|
T3 |
10 |
|
T15 |
2 |
|
T10 |
10 |
| true |
1467 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8796 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
258 |
1 |
|
T5 |
1 |
|
T64 |
2 |
|
T43 |
15 |
| others[2] |
268 |
1 |
|
T6 |
1 |
|
T43 |
7 |
|
T130 |
10 |
| others[3] |
428 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T9 |
1 |
| false |
137 |
1 |
|
T2 |
1 |
|
T43 |
7 |
|
T130 |
3 |
| true |
3099 |
1 |
|
T4 |
1 |
|
T10 |
81 |
|
T42 |
15 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9010 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T5 |
1 |
| others[1] |
453 |
1 |
|
T2 |
1 |
|
T10 |
7 |
|
T42 |
1 |
| others[2] |
442 |
1 |
|
T5 |
1 |
|
T10 |
13 |
|
T42 |
1 |
| others[3] |
736 |
1 |
|
T10 |
11 |
|
T16 |
1 |
|
T42 |
5 |
| false |
224 |
1 |
|
T10 |
4 |
|
T42 |
2 |
|
T64 |
1 |
| true |
2121 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T10 |
35 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8787 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T5 |
1 |
| others[1] |
253 |
1 |
|
T2 |
1 |
|
T43 |
16 |
|
T130 |
11 |
| others[2] |
260 |
1 |
|
T9 |
1 |
|
T43 |
12 |
|
T130 |
14 |
| others[3] |
387 |
1 |
|
T388 |
1 |
|
T43 |
11 |
|
T130 |
14 |
| false |
111 |
1 |
|
T43 |
4 |
|
T130 |
4 |
|
T90 |
2 |
| true |
3188 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T10 |
81 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8772 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T5 |
1 |
| others[1] |
262 |
1 |
|
T43 |
7 |
|
T130 |
12 |
|
T131 |
1 |
| others[2] |
240 |
1 |
|
T43 |
10 |
|
T130 |
12 |
|
T294 |
1 |
| others[3] |
388 |
1 |
|
T7 |
1 |
|
T17 |
1 |
|
T43 |
16 |
| false |
137 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
| true |
3187 |
1 |
|
T4 |
1 |
|
T10 |
81 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9312 |
1 |
|
T1 |
2 |
|
T3 |
62 |
|
T15 |
48 |
| others[1] |
784 |
1 |
|
T5 |
1 |
|
T10 |
18 |
|
T42 |
4 |
| others[2] |
771 |
1 |
|
T2 |
1 |
|
T10 |
15 |
|
T43 |
16 |
| others[3] |
1339 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T10 |
19 |
| false |
401 |
1 |
|
T10 |
6 |
|
T42 |
4 |
|
T64 |
1 |
| true |
379 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T21 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |