Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
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Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00
Crosses 16 0 16 100.00


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
erase_cp 2 0 2 100.00 100 1 1 0
op_cp 4 0 4 100.00 100 1 1 0
op_evict_cp 5 0 5 100.00 100 1 1 0
part_cp 4 0 4 100.00 100 1 1 0


Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
op_part_cross 16 0 16 100.00 100 1 1 0


Summary for Variable erase_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for erase_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashErasePage] 187444 1 T1 1 T2 165 T3 144
auto[FlashEraseBank] 221768 1 T2 35 T5 3 T6 1974



Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for op_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashOpRead] 228872 1 T1 1 T2 83 T3 42
auto[FlashOpProgram] 162065 1 T2 89 T3 61 T5 1
auto[FlashOpErase] 14275 1 T2 28 T3 41 T5 1
auto[FlashOpInvalid] 4000 1 T91 200 T145 200 T297 200



Summary for Variable op_evict_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for op_evict_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
op[FlashOpRead] 228872 1 T1 1 T2 83 T3 42
op[FlashOpProgram] 162065 1 T2 89 T3 61 T5 1
op[FlashOpErase] 14275 1 T2 28 T3 41 T5 1
read_erase_read 719 1 T2 3 T73 1 T43 3
read_prog_read 552 1 T2 12 T6 8 T64 5



Summary for Variable part_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for part_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashPartData] 291092 1 T1 1 T2 196 T3 144
auto[FlashPartInfo] 115160 1 T2 4 T15 294 T6 472
auto[FlashPartInfo1] 814 1 T6 3 T26 64 T17 1
auto[FlashPartInfo2] 2146 1 T6 20 T26 128 T16 11



Summary for Cross op_part_cross

Samples crossed: part_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for op_part_cross

Bins
part_cpop_cpCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashPartData] auto[FlashOpRead] 168743 1 T1 1 T2 80 T3 42
auto[FlashPartData] auto[FlashOpProgram] 114675 1 T2 89 T3 61 T5 1
auto[FlashPartData] auto[FlashOpErase] 3756 1 T2 27 T3 41 T5 1
auto[FlashPartData] auto[FlashOpInvalid] 3918 1 T91 196 T145 198 T297 200
auto[FlashPartInfo] auto[FlashOpRead] 58025 1 T2 3 T15 146 T6 232
auto[FlashPartInfo] auto[FlashOpProgram] 46583 1 T15 74 T6 240 T26 320
auto[FlashPartInfo] auto[FlashOpErase] 10484 1 T2 1 T15 74 T49 11
auto[FlashPartInfo] auto[FlashOpInvalid] 68 1 T91 4 T145 2 T147 4
auto[FlashPartInfo1] auto[FlashOpRead] 639 1 T6 3 T26 32 T17 1
auto[FlashPartInfo1] auto[FlashOpProgram] 165 1 T26 32 T151 1 T136 1
auto[FlashPartInfo1] auto[FlashOpErase] 4 1 T136 1 T140 1 T415 1
auto[FlashPartInfo1] auto[FlashOpInvalid] 6 1 T136 2 T415 2 T416 2
auto[FlashPartInfo2] auto[FlashOpRead] 1465 1 T6 5 T26 64 T16 11
auto[FlashPartInfo2] auto[FlashOpProgram] 642 1 T6 15 T26 64 T33 6
auto[FlashPartInfo2] auto[FlashOpErase] 31 1 T134 1 T148 1 T151 1
auto[FlashPartInfo2] auto[FlashOpInvalid] 8 1 T417 2 T418 2 T136 2

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