Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	6	26	81.25

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	6	26	81.25	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27506	1		T2	20		T15	148		T64	24
auto[1]	6	1		T362	3		T186	1		T83	1
auto[2]	16	1		T42	12		T166	4		-	-
auto[3]	54	1		T11	2		T48	1		T82	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	6897	1		T2	5		T15	37		T42	3
evic_idx[1]	6896	1		T2	5		T15	37		T42	3
evic_idx[2]	6893	1		T2	5		T15	37		T42	3
evic_idx[3]	6896	1		T2	5		T15	37		T42	3

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	26710	1		T15	148		T42	4		T91	400
evic_op[2]	303	1		T64	24		T43	8		T11	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	6	26	81.25	6

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[2]]	[auto[2]]	0	1	1
[evic_idx[1]]	[evic_op[1]]	[auto[1]]	0	1	1
[evic_idx[1]]	[evic_op[2]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[2] , evic_idx[3]]	[evic_op[2]]	[auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6668	1		T15	37		T91	100		T145	100
evic_idx[0]	evic_op[1]	auto[1]	1	1		T362	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	1	1		T42	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	9	1		T155	2		T363	1		T364	4
evic_idx[0]	evic_op[2]	auto[0]	69	1		T64	6		T43	2		T88	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T365	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	5	1		T11	1		T207	1		T366	1
evic_idx[1]	evic_op[1]	auto[0]	6668	1		T15	37		T91	100		T145	100
evic_idx[1]	evic_op[1]	auto[2]	1	1		T42	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	8	1		T155	2		T363	1		T364	4
evic_idx[1]	evic_op[2]	auto[0]	69	1		T64	6		T43	2		T88	1
evic_idx[1]	evic_op[2]	auto[3]	7	1		T185	1		T207	1		T367	1
evic_idx[2]	evic_op[1]	auto[0]	6668	1		T15	37		T91	100		T145	100
evic_idx[2]	evic_op[1]	auto[1]	1	1		T362	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	1	1		T42	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	6	1		T363	1		T364	4		T368	1
evic_idx[2]	evic_op[2]	auto[0]	70	1		T64	6		T43	2		T88	1
evic_idx[2]	evic_op[2]	auto[1]	1	1		T186	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	4	1		T369	1		T370	1		T371	1
evic_idx[3]	evic_op[1]	auto[0]	6668	1		T15	37		T91	100		T145	100
evic_idx[3]	evic_op[1]	auto[1]	1	1		T362	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	1	1		T42	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	8	1		T155	1		T363	1		T364	4
evic_idx[3]	evic_op[2]	auto[0]	69	1		T64	6		T43	2		T88	1
evic_idx[3]	evic_op[2]	auto[1]	1	1		T83	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	7	1		T11	1		T48	1		T82	1