Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	7325	1		T162	7325		-	-		-	-
rd_lvl[2]	25505	1		T162	3331		T163	4788		T312	1077
rd_lvl[3]	9146	1		T163	382		T353	2588		T312	1207
rd_lvl[4]	27739	1		T354	2307		T353	1407		T355	2313
rd_lvl[5]	19421	1		T264	1363		T354	693		T355	819
rd_lvl[6]	9893	1		T264	644		T312	562		T356	1331
rd_lvl[7]	10115	1		T12	935		T14	1371		T264	58
rd_lvl[8]	16355	1		T12	537		T14	1040		T264	83
rd_lvl[9]	9007	1		T14	52		T357	309		T358	593
rd_lvl[10]	7022	1		T14	51		T358	96		T359	555
rd_lvl[11]	3454	1		T264	83		T258	7		T298	595
rd_lvl[12]	6529	1		T303	255		T360	453		T298	402
rd_lvl[13]	5854	1		T13	665		T85	355		T303	620
rd_lvl[14]	4847	1		T13	367		T85	704		T360	1
rd_lvl[15]	4222	1		T86	458		T303	68		T361	453