Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	238643	1		T1	1		T2	2		T3	1
all_pins[1]	238643	1		T1	1		T2	2		T3	1
all_pins[2]	238643	1		T1	1		T2	2		T3	1
all_pins[3]	238643	1		T1	1		T2	2		T3	1
all_pins[4]	238643	1		T1	1		T2	2		T3	1
all_pins[5]	238643	1		T1	1		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1179097	1		T1	6		T2	12		T3	6
values[0x1]	252761	1		T12	2208		T13	2156		T14	3772
transitions[0x0=>0x1]	225287	1		T12	2208		T13	2156		T14	3720
transitions[0x1=>0x0]	225271	1		T12	2208		T13	2156		T14	3720

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	238473	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	170	1		T234	4		T235	4		T236	7
all_pins[0]	transitions[0x0=>0x1]	87	1		T234	1		T236	4		T348	3
all_pins[0]	transitions[0x1=>0x0]	93	1		T234	3		T235	1		T236	1
all_pins[1]	values[0x0]	238467	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	176	1		T234	6		T235	5		T236	4
all_pins[1]	transitions[0x0=>0x1]	149	1		T234	4		T235	5		T236	4
all_pins[1]	transitions[0x1=>0x0]	2500	1		T86	477		T361	449		T299	480
all_pins[2]	values[0x0]	236116	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	2527	1		T86	477		T361	449		T299	480
all_pins[2]	transitions[0x0=>0x1]	39	1		T234	1		T236	1		T348	1
all_pins[2]	transitions[0x1=>0x0]	167403	1		T12	1472		T13	1078		T14	2514
all_pins[3]	values[0x0]	68752	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	169891	1		T12	1472		T13	1078		T14	2514
all_pins[3]	transitions[0x0=>0x1]	145073	1		T12	1472		T13	1078		T14	2462
all_pins[3]	transitions[0x1=>0x0]	55109	1		T12	736		T13	1078		T14	1206
all_pins[4]	values[0x0]	158716	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	79927	1		T12	736		T13	1078		T14	1258
all_pins[4]	transitions[0x0=>0x1]	79912	1		T12	736		T13	1078		T14	1258
all_pins[4]	transitions[0x1=>0x0]	55	1		T234	2		T348	2		T352	1
all_pins[5]	values[0x0]	238573	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	70	1		T234	3		T235	1		T236	2
all_pins[5]	transitions[0x0=>0x1]	27	1		T234	1		T347	1		T350	1
all_pins[5]	transitions[0x1=>0x0]	111	1		T234	1		T235	3		T236	5