Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1		T234	7		T235	4		T236	7
all_values[1]	287	1		T234	7		T235	4		T236	7
all_values[2]	287	1		T234	7		T235	4		T236	7
all_values[3]	287	1		T234	7		T235	4		T236	7
all_values[4]	287	1		T234	7		T235	4		T236	7
all_values[5]	287	1		T234	7		T235	4		T236	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	909	1		T234	15		T235	12		T236	18
auto[1]	813	1		T234	27		T235	12		T236	24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	561	1		T234	11		T235	10		T236	11
auto[1]	1161	1		T234	31		T235	14		T236	31

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1002	1		T234	20		T235	17		T236	22
auto[1]	720	1		T234	22		T235	7		T236	20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	81	1		T234	4		T235	2		T236	1
all_values[0]	auto[0]	auto[1]	auto[1]	83	1		T234	1		T235	2		T236	4
all_values[0]	auto[1]	auto[0]	auto[1]	73	1		T234	1		T347	1		T348	1
all_values[0]	auto[1]	auto[1]	auto[1]	50	1		T234	1		T236	2		T348	4
all_values[1]	auto[0]	auto[0]	auto[1]	85	1		T236	1		T347	1		T348	2
all_values[1]	auto[0]	auto[1]	auto[1]	77	1		T234	2		T235	1		T236	1
all_values[1]	auto[1]	auto[0]	auto[1]	55	1		T234	1		T235	1		T236	4
all_values[1]	auto[1]	auto[1]	auto[1]	70	1		T234	4		T235	2		T236	1
all_values[2]	auto[0]	auto[0]	auto[0]	104	1		T234	2		T235	2		T236	3
all_values[2]	auto[0]	auto[1]	auto[0]	63	1		T234	1		T235	2		T236	1
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T234	1		T236	2		T347	1
all_values[2]	auto[1]	auto[1]	auto[1]	60	1		T234	3		T236	1		T348	1
all_values[3]	auto[0]	auto[0]	auto[0]	93	1		T235	4		T236	1		T347	1
all_values[3]	auto[0]	auto[1]	auto[0]	79	1		T234	3		T236	1		T347	2
all_values[3]	auto[1]	auto[0]	auto[1]	57	1		T347	1		T348	2		T349	3
all_values[3]	auto[1]	auto[1]	auto[1]	58	1		T234	4		T236	5		T348	1
all_values[4]	auto[0]	auto[0]	auto[0]	60	1		T234	2		T236	2		T348	1
all_values[4]	auto[0]	auto[0]	auto[1]	28	1		T348	1		T350	1		T351	2
all_values[4]	auto[0]	auto[1]	auto[0]	50	1		T234	2		T236	1		T347	1
all_values[4]	auto[0]	auto[1]	auto[1]	31	1		T235	2		T236	2		T347	1
all_values[4]	auto[1]	auto[0]	auto[1]	60	1		T234	1		T235	1		T236	1
all_values[4]	auto[1]	auto[1]	auto[1]	58	1		T234	2		T235	1		T236	1
all_values[5]	auto[0]	auto[0]	auto[0]	64	1		T234	1		T235	1		T352	1
all_values[5]	auto[0]	auto[0]	auto[1]	33	1		T234	1		T236	2		T348	2
all_values[5]	auto[0]	auto[1]	auto[0]	48	1		T235	1		T236	2		T348	1
all_values[5]	auto[0]	auto[1]	auto[1]	23	1		T234	1		T347	1		T348	1
all_values[5]	auto[1]	auto[0]	auto[1]	56	1		T234	1		T235	1		T236	1
all_values[5]	auto[1]	auto[1]	auto[1]	63	1		T234	3		T235	1		T236	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal