Unified Coverage Report

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmRdFifoRptrCheck_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmRdFifoWptrCheck_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	363973204	0	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	363973204	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	363973204	0	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	363973204	0	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	363973204	0	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	363973204	0	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	363973204	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	363973204	0	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	363973204	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	363973204	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	363973204	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	363973204	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	363973204	0	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	363973204	0	0	868
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	363973204	0	0	868
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	363973204	0	0	868
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	363973204	0	0	868
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	363973204	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	363973204	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	363973204	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	363973204	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	363973204	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	363973204	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	363973204	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	363973204	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	873	873	0	0
tb.dut.FlashAddrKnown_A	0	0	363973204	249185859	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	363973204	363298255	0	0
tb.dut.FlashKnownO_A	0	0	363973204	363298255	0	0
tb.dut.FlashProgKnown_A	0	0	363973204	130894220	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	363973204	363298255	0	0
tb.dut.IntrErrO_A	0	0	363973204	363298255	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	363973204	363298255	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	363973204	363298255	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	363973204	363298255	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	363973204	363298255	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	363973204	363298255	0	0
tb.dut.MemRspPayLoad_A	0	0	363973204	5036727	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	363973204	363298255	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	363973204	363298255	0	0
tb.dut.MemTlDValidKnownO_A	0	0	363973204	363298255	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	363973204	363298255	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	363973204	363298255	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	363973204	363298255	0	0
tb.dut.RspPayLoad_A	0	0	363973204	38694503	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	363973204	363298255	0	0
tb.dut.TdoEnIsOne_A	0	0	363973204	363298255	0	0
tb.dut.TdoKnown_A	0	0	363973204	363298255	0	0
tb.dut.TlAReadyKnownO_A	0	0	363973204	363298255	0	0
tb.dut.TlDValidKnownO_A	0	0	363973204	363298255	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	366472112	3184	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	366472112	762	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	366472112	1565	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	366472112	1666	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	366472112	1598	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	366472112	1420	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	366472112	1575	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	366472112	1646	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	366472112	1457	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	366472112	1381	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	366472112	1728	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	366472112	1425	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	366472112	653	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	366472112	663	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	366472112	777	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	366472112	603	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	366472112	751	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	366472112	905	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	366472112	839	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	366472112	705	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	366472112	705	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	366472112	681	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	366472112	1380	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	366472112	791	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	366472112	1626	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	366472112	1550	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	366472112	707	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	366472112	725	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	366472112	1632	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	366472112	1623	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	366472112	1844	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	366472112	1683	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	366472112	1549	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	366472112	1823	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	366472112	1886	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	366472112	1680	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	366472112	1345	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	366472112	1617	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	366472112	728	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	366472112	798	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	366472112	744	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	366472112	666	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	366472112	836	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	366472112	746	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	366472112	759	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	366472112	727	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	366472112	716	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	366472112	775	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	366472112	1585	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	366472112	772	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	366472112	1575	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	366472112	1363	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	366472112	793	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	366472112	708	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	366472112	833	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	366472112	1666	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	366472112	716	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	366472112	833	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	366472112	660	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	366472112	913	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	366472112	1467	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	366472112	930	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	366472112	841	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	366472112	955	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	366472112	837	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	366472112	900	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	366472112	945	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	366472112	864	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	366472112	934	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	366472112	1521	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	366472112	1571	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	366472112	1573	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	366472112	1292	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	366472112	1524	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	366472112	1450	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	366472112	1599	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	366472112	1780	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	366472112	174	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	366472112	719	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	366472112	660	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	366472112	762	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	366472112	702	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	366472112	899	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	366472112	746	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	366472112	715	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	366472112	779	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	366472112	756	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	366471966	27266075	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	366471966	365703081	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	366471966	365703081	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	366471966	39334557	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	366471966	365703081	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	366471966	365703081	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
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tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
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tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
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tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
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tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
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tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
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tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
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tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
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tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	1083	1083	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	992	0	10
Category 0	992	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	992	0	10
Severity 0	992	0	10

	NUMBER	PERCENT
Total Number	992	100.00
Uncovered	51	5.14
Success	941	94.86
Failure	0	0.00
Incomplete	15	1.51
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	2	20.00
All Matches	8	80.00
First Matches	8	80.00