Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	293116	1		T1	1		T2	2		T3	1
all_values[1]	293116	1		T1	1		T2	2		T3	1
all_values[2]	293116	1		T1	1		T2	2		T3	1
all_values[3]	293116	1		T1	1		T2	2		T3	1
all_values[4]	293116	1		T1	1		T2	2		T3	1
all_values[5]	293116	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	591709	1		T1	6		T2	12		T3	6
auto[1]	1166987	1		T14	17664		T15	5848		T16	8024

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	860491	1		T1	4		T2	7		T3	4
auto[1]	898205	1		T1	2		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	292971	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	145	1		T265	4		T266	6		T323	1
all_values[1]	auto[0]	auto[1]	292950	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	166	1		T264	1		T265	6		T266	3
all_values[2]	auto[0]	auto[0]	1399	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	64	1		T264	1		T265	1		T266	1
all_values[2]	auto[1]	auto[0]	291601	1		T14	4416		T15	1462		T16	2006
all_values[2]	auto[1]	auto[1]	52	1		T264	1		T265	2		T266	1
all_values[3]	auto[0]	auto[0]	1384	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	48	1		T264	1		T265	1		T266	2
all_values[3]	auto[1]	auto[0]	56104	1		T14	63		T15	731		T16	1001
all_values[3]	auto[1]	auto[1]	235580	1		T14	4353		T15	731		T16	1005
all_values[4]	auto[0]	auto[0]	983	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	457	1		T2	1		T6	1		T7	1
all_values[4]	auto[1]	auto[0]	216064	1		T14	3327		T15	731		T16	1001
all_values[4]	auto[1]	auto[1]	75612	1		T14	1089		T15	731		T16	1005
all_values[5]	auto[0]	auto[0]	1349	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	104	1		T78	1		T43	1		T79	1
all_values[5]	auto[1]	auto[0]	291607	1		T14	4416		T15	1462		T16	2006
all_values[5]	auto[1]	auto[1]	56	1		T264	1		T265	3		T323	3