Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T39 |
3 |
|
T129 |
3 |
|
T142 |
2 |
| others[1] |
105 |
1 |
|
T11 |
1 |
|
T67 |
1 |
|
T39 |
5 |
| others[2] |
126 |
1 |
|
T80 |
1 |
|
T39 |
4 |
|
T129 |
2 |
| others[3] |
164 |
1 |
|
T11 |
1 |
|
T39 |
8 |
|
T191 |
1 |
| false |
61 |
1 |
|
T67 |
1 |
|
T80 |
1 |
|
T39 |
2 |
| true |
6110 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T18 |
1 |
|
T39 |
10 |
|
T129 |
5 |
| others[1] |
238 |
1 |
|
T80 |
1 |
|
T39 |
8 |
|
T129 |
11 |
| others[2] |
243 |
1 |
|
T67 |
1 |
|
T39 |
11 |
|
T191 |
1 |
| others[3] |
397 |
1 |
|
T17 |
1 |
|
T39 |
18 |
|
T129 |
16 |
| false |
111 |
1 |
|
T14 |
1 |
|
T80 |
1 |
|
T39 |
5 |
| true |
5474 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
973 |
1 |
|
T63 |
3 |
|
T64 |
11 |
|
T39 |
17 |
| others[1] |
1072 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T5 |
1 |
| others[2] |
1060 |
1 |
|
T56 |
1 |
|
T63 |
1 |
|
T64 |
6 |
| others[3] |
1714 |
1 |
|
T11 |
1 |
|
T76 |
1 |
|
T63 |
2 |
| false |
536 |
1 |
|
T11 |
1 |
|
T8 |
1 |
|
T18 |
1 |
| true |
1311 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T39 |
14 |
|
T129 |
12 |
|
T193 |
1 |
| others[1] |
220 |
1 |
|
T80 |
1 |
|
T39 |
5 |
|
T191 |
1 |
| others[2] |
240 |
1 |
|
T17 |
1 |
|
T78 |
1 |
|
T14 |
1 |
| others[3] |
368 |
1 |
|
T31 |
1 |
|
T80 |
1 |
|
T12 |
1 |
| false |
133 |
1 |
|
T11 |
1 |
|
T39 |
4 |
|
T129 |
6 |
| true |
5495 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T39 |
10 |
|
T129 |
11 |
|
T142 |
9 |
| others[1] |
218 |
1 |
|
T6 |
1 |
|
T18 |
1 |
|
T39 |
11 |
| others[2] |
236 |
1 |
|
T39 |
12 |
|
T129 |
10 |
|
T193 |
1 |
| others[3] |
368 |
1 |
|
T11 |
1 |
|
T30 |
1 |
|
T78 |
1 |
| false |
114 |
1 |
|
T39 |
3 |
|
T129 |
6 |
|
T142 |
6 |
| true |
5497 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T8 |
1 |
| others[1] |
1214 |
1 |
|
T11 |
1 |
|
T63 |
2 |
|
T64 |
8 |
| others[2] |
1197 |
1 |
|
T63 |
1 |
|
T64 |
5 |
|
T39 |
16 |
| others[3] |
2065 |
1 |
|
T6 |
1 |
|
T25 |
1 |
|
T64 |
13 |
| false |
631 |
1 |
|
T63 |
2 |
|
T64 |
4 |
|
T9 |
1 |
| true |
309 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1195 |
1 |
|
T63 |
1 |
|
T64 |
12 |
|
T67 |
1 |
| others[1] |
1249 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T25 |
1 |
| others[2] |
1217 |
1 |
|
T63 |
1 |
|
T64 |
5 |
|
T39 |
18 |
| others[3] |
2048 |
1 |
|
T11 |
1 |
|
T8 |
1 |
|
T63 |
3 |
| false |
665 |
1 |
|
T6 |
1 |
|
T64 |
5 |
|
T68 |
1 |
| true |
292 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T80 |
1 |
|
T39 |
8 |
|
T129 |
3 |
| others[1] |
110 |
1 |
|
T6 |
1 |
|
T67 |
1 |
|
T80 |
1 |
| others[2] |
127 |
1 |
|
T11 |
1 |
|
T30 |
1 |
|
T39 |
7 |
| others[3] |
189 |
1 |
|
T18 |
1 |
|
T67 |
1 |
|
T39 |
7 |
| false |
49 |
1 |
|
T11 |
1 |
|
T39 |
3 |
|
T192 |
1 |
| true |
6080 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T18 |
1 |
|
T39 |
4 |
|
T192 |
1 |
| others[1] |
209 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T30 |
1 |
| others[2] |
213 |
1 |
|
T80 |
1 |
|
T39 |
10 |
|
T129 |
10 |
| others[3] |
406 |
1 |
|
T67 |
1 |
|
T12 |
1 |
|
T39 |
19 |
| false |
136 |
1 |
|
T39 |
7 |
|
T129 |
2 |
|
T142 |
10 |
| true |
5458 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1037 |
1 |
|
T63 |
2 |
|
T64 |
5 |
|
T9 |
1 |
| others[1] |
1067 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T22 |
1 |
| others[2] |
999 |
1 |
|
T11 |
1 |
|
T8 |
1 |
|
T63 |
1 |
| others[3] |
1696 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T25 |
1 |
| false |
536 |
1 |
|
T11 |
1 |
|
T31 |
1 |
|
T64 |
4 |
| true |
1331 |
1 |
|
T17 |
1 |
|
T56 |
1 |
|
T76 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T31 |
1 |
|
T39 |
8 |
|
T192 |
1 |
| others[1] |
237 |
1 |
|
T30 |
1 |
|
T39 |
9 |
|
T192 |
1 |
| others[2] |
233 |
1 |
|
T17 |
1 |
|
T39 |
12 |
|
T129 |
10 |
| others[3] |
368 |
1 |
|
T80 |
1 |
|
T39 |
19 |
|
T129 |
13 |
| false |
118 |
1 |
|
T11 |
1 |
|
T39 |
8 |
|
T129 |
8 |
| true |
5496 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T39 |
4 |
|
T129 |
11 |
|
T142 |
11 |
| others[1] |
230 |
1 |
|
T67 |
1 |
|
T39 |
10 |
|
T129 |
10 |
| others[2] |
249 |
1 |
|
T11 |
1 |
|
T39 |
17 |
|
T192 |
1 |
| others[3] |
333 |
1 |
|
T30 |
1 |
|
T78 |
1 |
|
T67 |
1 |
| false |
120 |
1 |
|
T11 |
1 |
|
T31 |
1 |
|
T80 |
1 |
| true |
5528 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T11 |
1 |
|
T64 |
3 |
|
T67 |
1 |
| others[1] |
1284 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T63 |
2 |
| others[2] |
1230 |
1 |
|
T25 |
1 |
|
T63 |
1 |
|
T64 |
12 |
| others[3] |
1985 |
1 |
|
T11 |
1 |
|
T30 |
1 |
|
T63 |
3 |
| false |
610 |
1 |
|
T6 |
1 |
|
T63 |
1 |
|
T64 |
4 |
| true |
311 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T25 |
1 |
|
T63 |
2 |
|
T64 |
6 |
| others[1] |
1207 |
1 |
|
T6 |
1 |
|
T76 |
1 |
|
T30 |
1 |
| others[2] |
1197 |
1 |
|
T17 |
1 |
|
T63 |
2 |
|
T64 |
8 |
| others[3] |
2110 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T8 |
1 |
| false |
647 |
1 |
|
T11 |
1 |
|
T64 |
4 |
|
T354 |
1 |
| true |
282 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
126 |
1 |
|
T17 |
1 |
|
T39 |
5 |
|
T129 |
7 |
| others[1] |
112 |
1 |
|
T80 |
1 |
|
T39 |
2 |
|
T129 |
4 |
| others[2] |
118 |
1 |
|
T11 |
1 |
|
T80 |
1 |
|
T39 |
2 |
| others[3] |
165 |
1 |
|
T6 |
1 |
|
T67 |
2 |
|
T39 |
8 |
| false |
52 |
1 |
|
T11 |
1 |
|
T39 |
1 |
|
T192 |
1 |
| true |
6093 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T39 |
10 |
|
T129 |
9 |
|
T142 |
8 |
| others[1] |
243 |
1 |
|
T78 |
1 |
|
T18 |
1 |
|
T80 |
1 |
| others[2] |
209 |
1 |
|
T13 |
1 |
|
T39 |
5 |
|
T129 |
14 |
| others[3] |
381 |
1 |
|
T39 |
20 |
|
T192 |
1 |
|
T129 |
13 |
| false |
122 |
1 |
|
T6 |
1 |
|
T39 |
5 |
|
T129 |
3 |
| true |
5493 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1029 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T64 |
7 |
| others[1] |
988 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T31 |
1 |
| others[2] |
1061 |
1 |
|
T56 |
1 |
|
T25 |
1 |
|
T8 |
1 |
| others[3] |
1722 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T11 |
1 |
| false |
539 |
1 |
|
T11 |
1 |
|
T76 |
1 |
|
T63 |
1 |
| true |
1327 |
1 |
|
T17 |
1 |
|
T12 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T14 |
1 |
|
T39 |
7 |
|
T129 |
8 |
| others[1] |
214 |
1 |
|
T17 |
1 |
|
T39 |
6 |
|
T129 |
10 |
| others[2] |
215 |
1 |
|
T6 |
1 |
|
T31 |
1 |
|
T39 |
7 |
| others[3] |
363 |
1 |
|
T80 |
1 |
|
T39 |
13 |
|
T192 |
1 |
| false |
125 |
1 |
|
T39 |
3 |
|
T129 |
6 |
|
T142 |
5 |
| true |
5542 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T80 |
1 |
|
T39 |
5 |
|
T129 |
15 |
| others[1] |
256 |
1 |
|
T18 |
1 |
|
T31 |
1 |
|
T39 |
15 |
| others[2] |
217 |
1 |
|
T39 |
14 |
|
T129 |
10 |
|
T142 |
10 |
| others[3] |
361 |
1 |
|
T11 |
2 |
|
T17 |
1 |
|
T39 |
11 |
| false |
109 |
1 |
|
T30 |
1 |
|
T39 |
4 |
|
T129 |
7 |
| true |
5519 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1282 |
1 |
|
T5 |
1 |
|
T63 |
1 |
|
T64 |
3 |
| others[1] |
1198 |
1 |
|
T6 |
1 |
|
T64 |
5 |
|
T67 |
2 |
| others[2] |
1221 |
1 |
|
T8 |
1 |
|
T63 |
3 |
|
T64 |
7 |
| others[3] |
2053 |
1 |
|
T11 |
2 |
|
T63 |
1 |
|
T64 |
17 |
| false |
597 |
1 |
|
T25 |
1 |
|
T63 |
2 |
|
T64 |
4 |
| true |
315 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T63 |
2 |
|
T64 |
10 |
|
T68 |
1 |
| others[1] |
1257 |
1 |
|
T11 |
1 |
|
T63 |
3 |
|
T64 |
6 |
| others[2] |
1262 |
1 |
|
T6 |
1 |
|
T25 |
1 |
|
T63 |
2 |
| others[3] |
2037 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T64 |
8 |
| false |
591 |
1 |
|
T11 |
1 |
|
T64 |
4 |
|
T39 |
10 |
| true |
300 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T67 |
1 |
|
T39 |
3 |
|
T129 |
5 |
| others[1] |
83 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T67 |
1 |
| others[2] |
111 |
1 |
|
T80 |
1 |
|
T39 |
5 |
|
T191 |
1 |
| others[3] |
194 |
1 |
|
T11 |
1 |
|
T39 |
15 |
|
T192 |
1 |
| false |
52 |
1 |
|
T80 |
1 |
|
T39 |
1 |
|
T129 |
5 |
| true |
6117 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T18 |
1 |
|
T39 |
7 |
|
T129 |
9 |
| others[1] |
229 |
1 |
|
T39 |
13 |
|
T129 |
11 |
|
T142 |
10 |
| others[2] |
226 |
1 |
|
T2 |
1 |
|
T30 |
1 |
|
T67 |
1 |
| others[3] |
374 |
1 |
|
T39 |
16 |
|
T129 |
12 |
|
T142 |
16 |
| false |
123 |
1 |
|
T14 |
1 |
|
T39 |
6 |
|
T129 |
6 |
| true |
5481 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1103 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T64 |
7 |
| others[1] |
980 |
1 |
|
T11 |
1 |
|
T63 |
2 |
|
T64 |
6 |
| others[2] |
1077 |
1 |
|
T63 |
1 |
|
T64 |
7 |
|
T68 |
1 |
| others[3] |
1678 |
1 |
|
T4 |
1 |
|
T11 |
1 |
|
T63 |
2 |
| false |
498 |
1 |
|
T17 |
1 |
|
T8 |
1 |
|
T78 |
1 |
| true |
1330 |
1 |
|
T2 |
1 |
|
T22 |
1 |
|
T56 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T78 |
1 |
|
T39 |
12 |
|
T129 |
12 |
| others[1] |
240 |
1 |
|
T18 |
1 |
|
T39 |
9 |
|
T129 |
13 |
| others[2] |
241 |
1 |
|
T6 |
1 |
|
T67 |
1 |
|
T39 |
13 |
| others[3] |
371 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T39 |
14 |
| false |
128 |
1 |
|
T2 |
1 |
|
T39 |
3 |
|
T129 |
5 |
| true |
5483 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T18 |
1 |
|
T39 |
7 |
|
T129 |
7 |
| others[1] |
236 |
1 |
|
T67 |
1 |
|
T80 |
1 |
|
T39 |
10 |
| others[2] |
209 |
1 |
|
T39 |
10 |
|
T129 |
8 |
|
T142 |
10 |
| others[3] |
368 |
1 |
|
T6 |
1 |
|
T31 |
1 |
|
T39 |
16 |
| false |
108 |
1 |
|
T11 |
1 |
|
T30 |
1 |
|
T39 |
5 |
| true |
5525 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T63 |
1 |
|
T64 |
6 |
|
T67 |
1 |
| others[1] |
1205 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T64 |
7 |
| others[2] |
1187 |
1 |
|
T11 |
1 |
|
T63 |
3 |
|
T64 |
6 |
| others[3] |
2068 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T25 |
1 |
| false |
637 |
1 |
|
T63 |
2 |
|
T64 |
4 |
|
T39 |
4 |
| true |
319 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T63 |
1 |
|
T64 |
4 |
|
T67 |
2 |
| others[1] |
1244 |
1 |
|
T11 |
1 |
|
T63 |
4 |
|
T64 |
4 |
| others[2] |
1209 |
1 |
|
T64 |
7 |
|
T9 |
1 |
|
T68 |
1 |
| others[3] |
2066 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T5 |
1 |
| false |
635 |
1 |
|
T8 |
1 |
|
T63 |
1 |
|
T64 |
3 |
| true |
294 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T39 |
5 |
|
T191 |
1 |
|
T129 |
2 |
| others[1] |
99 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T17 |
1 |
| others[2] |
96 |
1 |
|
T67 |
1 |
|
T80 |
1 |
|
T39 |
4 |
| others[3] |
186 |
1 |
|
T11 |
1 |
|
T39 |
4 |
|
T129 |
3 |
| false |
42 |
1 |
|
T2 |
1 |
|
T67 |
1 |
|
T39 |
3 |
| true |
6136 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T6 |
1 |
|
T39 |
14 |
|
T129 |
7 |
| others[1] |
213 |
1 |
|
T18 |
1 |
|
T31 |
1 |
|
T13 |
1 |
| others[2] |
248 |
1 |
|
T39 |
9 |
|
T129 |
12 |
|
T142 |
11 |
| others[3] |
370 |
1 |
|
T11 |
2 |
|
T17 |
1 |
|
T30 |
1 |
| false |
110 |
1 |
|
T39 |
3 |
|
T129 |
3 |
|
T142 |
2 |
| true |
5483 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1037 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
| others[1] |
1024 |
1 |
|
T6 |
1 |
|
T25 |
1 |
|
T18 |
1 |
| others[2] |
1014 |
1 |
|
T76 |
1 |
|
T30 |
1 |
|
T14 |
1 |
| others[3] |
1775 |
1 |
|
T11 |
2 |
|
T22 |
1 |
|
T63 |
4 |
| false |
530 |
1 |
|
T63 |
1 |
|
T64 |
2 |
|
T39 |
11 |
| true |
1286 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T56 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |