Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1254 |
1 |
|
T25 |
1 |
|
T64 |
9 |
|
T68 |
1 |
| others[1] |
1197 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T63 |
2 |
| others[2] |
1249 |
1 |
|
T8 |
1 |
|
T63 |
2 |
|
T64 |
6 |
| others[3] |
2033 |
1 |
|
T6 |
1 |
|
T11 |
2 |
|
T63 |
2 |
| false |
640 |
1 |
|
T63 |
1 |
|
T64 |
6 |
|
T39 |
8 |
| true |
293 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T67 |
1 |
|
T39 |
6 |
|
T129 |
3 |
| others[1] |
107 |
1 |
|
T39 |
4 |
|
T191 |
1 |
|
T129 |
2 |
| others[2] |
104 |
1 |
|
T17 |
1 |
|
T67 |
1 |
|
T80 |
1 |
| others[3] |
161 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T80 |
1 |
| false |
59 |
1 |
|
T11 |
1 |
|
T39 |
1 |
|
T192 |
1 |
| true |
6132 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T12 |
1 |
|
T39 |
8 |
|
T192 |
1 |
| others[1] |
220 |
1 |
|
T17 |
1 |
|
T39 |
4 |
|
T192 |
1 |
| others[2] |
238 |
1 |
|
T18 |
1 |
|
T80 |
1 |
|
T39 |
15 |
| others[3] |
397 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T67 |
1 |
| false |
123 |
1 |
|
T39 |
7 |
|
T129 |
5 |
|
T142 |
4 |
| true |
5447 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1020 |
1 |
|
T17 |
1 |
|
T25 |
1 |
|
T64 |
9 |
| others[1] |
1059 |
1 |
|
T11 |
1 |
|
T76 |
1 |
|
T63 |
1 |
| others[2] |
1042 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T11 |
1 |
| others[3] |
1677 |
1 |
|
T22 |
1 |
|
T8 |
1 |
|
T78 |
1 |
| false |
530 |
1 |
|
T64 |
5 |
|
T67 |
1 |
|
T39 |
14 |
| true |
1338 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T56 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T80 |
2 |
| others[1] |
216 |
1 |
|
T11 |
1 |
|
T78 |
1 |
|
T67 |
1 |
| others[2] |
207 |
1 |
|
T39 |
8 |
|
T129 |
6 |
|
T142 |
11 |
| others[3] |
336 |
1 |
|
T12 |
1 |
|
T39 |
14 |
|
T129 |
13 |
| false |
130 |
1 |
|
T39 |
7 |
|
T129 |
8 |
|
T193 |
1 |
| true |
5554 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T17 |
1 |
|
T39 |
10 |
|
T129 |
10 |
| others[1] |
192 |
1 |
|
T11 |
1 |
|
T39 |
13 |
|
T129 |
17 |
| others[2] |
244 |
1 |
|
T11 |
1 |
|
T39 |
8 |
|
T129 |
11 |
| others[3] |
365 |
1 |
|
T30 |
1 |
|
T18 |
1 |
|
T80 |
1 |
| false |
119 |
1 |
|
T67 |
2 |
|
T39 |
6 |
|
T192 |
1 |
| true |
5531 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1148 |
1 |
|
T25 |
1 |
|
T64 |
5 |
|
T10 |
1 |
| others[1] |
1242 |
1 |
|
T11 |
1 |
|
T63 |
2 |
|
T64 |
7 |
| others[2] |
1240 |
1 |
|
T6 |
1 |
|
T63 |
2 |
|
T64 |
3 |
| others[3] |
2091 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T8 |
1 |
| false |
634 |
1 |
|
T64 |
3 |
|
T39 |
16 |
|
T120 |
5 |
| true |
311 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T11 |
2 |
|
T63 |
2 |
|
T64 |
4 |
| others[1] |
1215 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T64 |
3 |
| others[2] |
1232 |
1 |
|
T64 |
9 |
|
T67 |
1 |
|
T10 |
1 |
| others[3] |
2059 |
1 |
|
T25 |
1 |
|
T63 |
5 |
|
T64 |
14 |
| false |
640 |
1 |
|
T6 |
1 |
|
T64 |
6 |
|
T39 |
5 |
| true |
286 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T6 |
1 |
|
T39 |
3 |
|
T192 |
1 |
| others[1] |
105 |
1 |
|
T11 |
2 |
|
T67 |
1 |
|
T39 |
4 |
| others[2] |
117 |
1 |
|
T67 |
1 |
|
T80 |
1 |
|
T191 |
1 |
| others[3] |
179 |
1 |
|
T31 |
1 |
|
T80 |
1 |
|
T39 |
12 |
| false |
62 |
1 |
|
T39 |
1 |
|
T142 |
3 |
|
T131 |
1 |
| true |
6096 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T17 |
1 |
|
T39 |
12 |
|
T129 |
7 |
| others[1] |
231 |
1 |
|
T14 |
1 |
|
T80 |
1 |
|
T39 |
12 |
| others[2] |
240 |
1 |
|
T6 |
1 |
|
T39 |
9 |
|
T129 |
8 |
| others[3] |
350 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T18 |
1 |
| false |
124 |
1 |
|
T11 |
1 |
|
T67 |
1 |
|
T39 |
5 |
| true |
5503 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1015 |
1 |
|
T11 |
1 |
|
T25 |
1 |
|
T64 |
11 |
| others[1] |
996 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T64 |
8 |
| others[2] |
1068 |
1 |
|
T76 |
1 |
|
T8 |
1 |
|
T63 |
2 |
| others[3] |
1715 |
1 |
|
T11 |
1 |
|
T22 |
1 |
|
T78 |
1 |
| false |
530 |
1 |
|
T63 |
1 |
|
T64 |
6 |
|
T39 |
11 |
| true |
1342 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T39 |
8 |
|
T191 |
1 |
|
T192 |
1 |
| others[1] |
226 |
1 |
|
T12 |
1 |
|
T39 |
8 |
|
T129 |
4 |
| others[2] |
234 |
1 |
|
T39 |
11 |
|
T129 |
10 |
|
T142 |
11 |
| others[3] |
375 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T31 |
1 |
| false |
101 |
1 |
|
T39 |
4 |
|
T129 |
5 |
|
T193 |
1 |
| true |
5489 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
184 |
1 |
|
T2 |
1 |
|
T39 |
8 |
|
T129 |
6 |
| others[1] |
199 |
1 |
|
T6 |
1 |
|
T18 |
1 |
|
T31 |
1 |
| others[2] |
222 |
1 |
|
T30 |
1 |
|
T67 |
1 |
|
T39 |
10 |
| others[3] |
385 |
1 |
|
T17 |
1 |
|
T78 |
1 |
|
T80 |
2 |
| false |
124 |
1 |
|
T11 |
1 |
|
T39 |
3 |
|
T129 |
2 |
| true |
5552 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1313 |
1 |
|
T17 |
1 |
|
T63 |
1 |
|
T64 |
7 |
| others[1] |
1211 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T63 |
3 |
| others[2] |
1229 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T63 |
1 |
| others[3] |
1945 |
1 |
|
T8 |
1 |
|
T63 |
2 |
|
T64 |
13 |
| false |
636 |
1 |
|
T25 |
1 |
|
T64 |
2 |
|
T39 |
10 |
| true |
332 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T63 |
3 |
| others[1] |
1231 |
1 |
|
T63 |
1 |
|
T64 |
7 |
|
T67 |
1 |
| others[2] |
1262 |
1 |
|
T5 |
1 |
|
T25 |
1 |
|
T63 |
2 |
| others[3] |
2017 |
1 |
|
T11 |
1 |
|
T63 |
1 |
|
T64 |
17 |
| false |
618 |
1 |
|
T8 |
1 |
|
T64 |
1 |
|
T80 |
2 |
| true |
290 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T11 |
1 |
|
T31 |
1 |
|
T39 |
1 |
| others[1] |
102 |
1 |
|
T30 |
1 |
|
T80 |
1 |
|
T39 |
2 |
| others[2] |
116 |
1 |
|
T67 |
1 |
|
T39 |
5 |
|
T129 |
3 |
| others[3] |
183 |
1 |
|
T11 |
1 |
|
T67 |
1 |
|
T80 |
1 |
| false |
67 |
1 |
|
T39 |
4 |
|
T129 |
3 |
|
T142 |
4 |
| true |
6092 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T30 |
1 |
|
T14 |
1 |
|
T80 |
1 |
| others[1] |
222 |
1 |
|
T6 |
1 |
|
T13 |
1 |
|
T39 |
11 |
| others[2] |
216 |
1 |
|
T11 |
1 |
|
T39 |
10 |
|
T129 |
8 |
| others[3] |
353 |
1 |
|
T39 |
14 |
|
T129 |
20 |
|
T142 |
13 |
| false |
132 |
1 |
|
T80 |
1 |
|
T39 |
7 |
|
T192 |
1 |
| true |
5510 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1058 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T17 |
1 |
| others[1] |
1018 |
1 |
|
T5 |
1 |
|
T30 |
1 |
|
T63 |
2 |
| others[2] |
1030 |
1 |
|
T56 |
1 |
|
T63 |
2 |
|
T64 |
5 |
| others[3] |
1704 |
1 |
|
T11 |
1 |
|
T8 |
1 |
|
T63 |
2 |
| false |
536 |
1 |
|
T31 |
1 |
|
T64 |
5 |
|
T80 |
1 |
| true |
1320 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T17 |
1 |
|
T80 |
1 |
|
T39 |
10 |
| others[1] |
236 |
1 |
|
T6 |
1 |
|
T39 |
10 |
|
T129 |
10 |
| others[2] |
231 |
1 |
|
T11 |
1 |
|
T78 |
1 |
|
T31 |
1 |
| others[3] |
372 |
1 |
|
T18 |
1 |
|
T80 |
1 |
|
T39 |
15 |
| false |
117 |
1 |
|
T39 |
10 |
|
T192 |
1 |
|
T129 |
3 |
| true |
5475 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T39 |
11 |
|
T129 |
13 |
|
T142 |
4 |
| others[1] |
238 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T31 |
1 |
| others[2] |
238 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T78 |
1 |
| others[3] |
333 |
1 |
|
T30 |
1 |
|
T67 |
1 |
|
T80 |
1 |
| false |
115 |
1 |
|
T39 |
3 |
|
T129 |
2 |
|
T142 |
5 |
| true |
5521 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1235 |
1 |
|
T6 |
1 |
|
T63 |
2 |
|
T64 |
4 |
| others[1] |
1176 |
1 |
|
T11 |
1 |
|
T64 |
8 |
|
T80 |
1 |
| others[2] |
1242 |
1 |
|
T11 |
1 |
|
T22 |
1 |
|
T63 |
1 |
| others[3] |
2046 |
1 |
|
T76 |
1 |
|
T25 |
1 |
|
T8 |
1 |
| false |
638 |
1 |
|
T5 |
1 |
|
T63 |
1 |
|
T64 |
7 |
| true |
329 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T76 |
1 |
| others[1] |
1239 |
1 |
|
T8 |
1 |
|
T63 |
1 |
|
T64 |
7 |
| others[2] |
1198 |
1 |
|
T63 |
2 |
|
T64 |
3 |
|
T80 |
1 |
| others[3] |
2026 |
1 |
|
T11 |
1 |
|
T25 |
1 |
|
T63 |
3 |
| false |
676 |
1 |
|
T6 |
1 |
|
T63 |
1 |
|
T64 |
4 |
| true |
300 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T31 |
1 |
|
T39 |
3 |
|
T129 |
4 |
| others[1] |
108 |
1 |
|
T11 |
1 |
|
T80 |
1 |
|
T39 |
3 |
| others[2] |
104 |
1 |
|
T67 |
1 |
|
T39 |
4 |
|
T192 |
1 |
| others[3] |
200 |
1 |
|
T11 |
1 |
|
T67 |
1 |
|
T80 |
1 |
| false |
57 |
1 |
|
T6 |
1 |
|
T39 |
1 |
|
T129 |
2 |
| true |
6093 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T39 |
14 |
|
T192 |
1 |
|
T129 |
8 |
| others[1] |
215 |
1 |
|
T2 |
1 |
|
T39 |
7 |
|
T129 |
6 |
| others[2] |
235 |
1 |
|
T80 |
1 |
|
T39 |
13 |
|
T129 |
4 |
| others[3] |
380 |
1 |
|
T78 |
1 |
|
T80 |
1 |
|
T39 |
17 |
| false |
137 |
1 |
|
T18 |
1 |
|
T39 |
5 |
|
T129 |
10 |
| true |
5472 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1018 |
1 |
|
T6 |
1 |
|
T63 |
1 |
|
T64 |
6 |
| others[1] |
1033 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
1 |
| others[2] |
1011 |
1 |
|
T56 |
1 |
|
T18 |
1 |
|
T63 |
3 |
| others[3] |
1744 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T25 |
1 |
| false |
531 |
1 |
|
T11 |
1 |
|
T78 |
1 |
|
T64 |
2 |
| true |
1329 |
1 |
|
T17 |
1 |
|
T22 |
1 |
|
T76 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T30 |
1 |
|
T12 |
1 |
|
T39 |
16 |
| others[1] |
229 |
1 |
|
T11 |
2 |
|
T67 |
1 |
|
T39 |
8 |
| others[2] |
211 |
1 |
|
T2 |
1 |
|
T39 |
7 |
|
T129 |
12 |
| others[3] |
362 |
1 |
|
T6 |
1 |
|
T78 |
1 |
|
T14 |
1 |
| false |
102 |
1 |
|
T39 |
4 |
|
T129 |
5 |
|
T142 |
2 |
| true |
5544 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T80 |
1 |
|
T39 |
11 |
|
T129 |
10 |
| others[1] |
208 |
1 |
|
T39 |
5 |
|
T129 |
19 |
|
T142 |
14 |
| others[2] |
235 |
1 |
|
T67 |
1 |
|
T39 |
13 |
|
T129 |
11 |
| others[3] |
354 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T39 |
17 |
| false |
88 |
1 |
|
T39 |
1 |
|
T129 |
6 |
|
T142 |
7 |
| true |
5561 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T11 |
1 |
|
T63 |
2 |
|
T64 |
7 |
| others[1] |
1238 |
1 |
|
T2 |
1 |
|
T63 |
4 |
|
T64 |
6 |
| others[2] |
1229 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T25 |
1 |
| others[3] |
1998 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T64 |
7 |
| false |
632 |
1 |
|
T64 |
6 |
|
T39 |
7 |
|
T81 |
3 |
| true |
322 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11 |
1 |
|
T22 |
1 |
|
T109 |
1 |
|
T89 |
1 |
| others[1] |
14 |
1 |
|
T92 |
1 |
|
T110 |
1 |
|
T355 |
1 |
| others[2] |
8 |
1 |
|
T93 |
1 |
|
T356 |
1 |
|
T251 |
1 |
| others[3] |
9 |
1 |
|
T48 |
1 |
|
T36 |
1 |
|
T111 |
1 |
| false |
3 |
1 |
|
T219 |
1 |
|
T357 |
1 |
|
T358 |
1 |
| true |
45 |
1 |
|
T23 |
1 |
|
T92 |
1 |
|
T89 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T65 |
1 |
|
T359 |
1 |
|
T360 |
1 |
| others[1] |
4 |
1 |
|
T361 |
1 |
|
T362 |
1 |
|
T363 |
1 |
| others[2] |
2 |
1 |
|
T364 |
1 |
|
T365 |
1 |
|
- |
- |
| others[3] |
4 |
1 |
|
T366 |
1 |
|
T367 |
1 |
|
T368 |
1 |
| false |
12 |
1 |
|
T86 |
1 |
|
T369 |
1 |
|
T370 |
1 |
| true |
21 |
1 |
|
T7 |
1 |
|
T208 |
1 |
|
T243 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T371 |
1 |
|
T372 |
1 |
|
- |
- |
| others[1] |
1 |
1 |
|
T373 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
1 |
1 |
|
T367 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
3 |
1 |
|
T368 |
1 |
|
T362 |
1 |
|
T374 |
1 |
| false |
11 |
1 |
|
T65 |
1 |
|
T243 |
1 |
|
T375 |
1 |
| true |
29 |
1 |
|
T7 |
1 |
|
T86 |
1 |
|
T208 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |