Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10198 |
1 |
|
T5 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
760 |
1 |
|
T11 |
1 |
|
T63 |
3 |
|
T64 |
8 |
| others[2] |
780 |
1 |
|
T6 |
1 |
|
T64 |
5 |
|
T80 |
1 |
| others[3] |
1325 |
1 |
|
T11 |
1 |
|
T76 |
1 |
|
T30 |
1 |
| false |
390 |
1 |
|
T8 |
1 |
|
T64 |
5 |
|
T39 |
14 |
| true |
407 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2464 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T24 |
45 |
| others[1] |
2340 |
1 |
|
T11 |
1 |
|
T24 |
34 |
|
T25 |
1 |
| others[2] |
2365 |
1 |
|
T24 |
27 |
|
T8 |
1 |
|
T30 |
1 |
| others[3] |
4050 |
1 |
|
T5 |
1 |
|
T24 |
66 |
|
T63 |
3 |
| false |
1181 |
1 |
|
T24 |
25 |
|
T78 |
1 |
|
T63 |
1 |
| true |
1460 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9649 |
1 |
|
T6 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
249 |
1 |
|
T354 |
1 |
|
T39 |
7 |
|
T192 |
1 |
| others[2] |
279 |
1 |
|
T67 |
1 |
|
T39 |
10 |
|
T191 |
1 |
| others[3] |
472 |
1 |
|
T2 |
1 |
|
T30 |
1 |
|
T13 |
1 |
| false |
123 |
1 |
|
T17 |
1 |
|
T39 |
4 |
|
T129 |
9 |
| true |
3088 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9891 |
1 |
|
T11 |
2 |
|
T17 |
1 |
|
T24 |
197 |
| others[1] |
450 |
1 |
|
T6 |
1 |
|
T76 |
1 |
|
T64 |
4 |
| others[2] |
432 |
1 |
|
T78 |
1 |
|
T63 |
1 |
|
T64 |
4 |
| others[3] |
758 |
1 |
|
T2 |
1 |
|
T22 |
1 |
|
T63 |
2 |
| false |
232 |
1 |
|
T63 |
1 |
|
T64 |
2 |
|
T12 |
1 |
| true |
2097 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T56 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9633 |
1 |
|
T11 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
255 |
1 |
|
T11 |
1 |
|
T8 |
1 |
|
T80 |
1 |
| others[2] |
253 |
1 |
|
T39 |
10 |
|
T129 |
17 |
|
T142 |
15 |
| others[3] |
446 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T31 |
1 |
| false |
124 |
1 |
|
T39 |
4 |
|
T128 |
1 |
|
T129 |
2 |
| true |
3149 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9660 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T24 |
197 |
| others[1] |
227 |
1 |
|
T18 |
1 |
|
T9 |
1 |
|
T39 |
9 |
| others[2] |
268 |
1 |
|
T8 |
1 |
|
T10 |
1 |
|
T39 |
11 |
| others[3] |
393 |
1 |
|
T2 |
1 |
|
T39 |
18 |
|
T192 |
1 |
| false |
121 |
1 |
|
T17 |
1 |
|
T39 |
4 |
|
T129 |
6 |
| true |
3191 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10240 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T63 |
2 |
| others[1] |
734 |
1 |
|
T5 |
1 |
|
T64 |
7 |
|
T39 |
17 |
| others[2] |
792 |
1 |
|
T63 |
1 |
|
T64 |
5 |
|
T10 |
1 |
| others[3] |
1339 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T63 |
2 |
| false |
372 |
1 |
|
T63 |
2 |
|
T64 |
3 |
|
T39 |
12 |
| true |
383 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10167 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T64 |
2 |
| others[1] |
769 |
1 |
|
T63 |
2 |
|
T64 |
8 |
|
T80 |
1 |
| others[2] |
770 |
1 |
|
T17 |
1 |
|
T8 |
1 |
|
T63 |
1 |
| others[3] |
1345 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T11 |
1 |
| false |
370 |
1 |
|
T63 |
2 |
|
T64 |
2 |
|
T10 |
1 |
| true |
400 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2341 |
1 |
|
T11 |
1 |
|
T24 |
52 |
|
T8 |
1 |
| others[1] |
2408 |
1 |
|
T5 |
1 |
|
T24 |
35 |
|
T63 |
2 |
| others[2] |
2332 |
1 |
|
T24 |
38 |
|
T63 |
3 |
|
T64 |
4 |
| others[3] |
4018 |
1 |
|
T11 |
1 |
|
T24 |
58 |
|
T25 |
1 |
| false |
1268 |
1 |
|
T24 |
14 |
|
T64 |
6 |
|
T39 |
8 |
| true |
1454 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9672 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T24 |
197 |
| others[1] |
234 |
1 |
|
T78 |
1 |
|
T18 |
1 |
|
T12 |
1 |
| others[2] |
255 |
1 |
|
T9 |
1 |
|
T39 |
5 |
|
T128 |
2 |
| others[3] |
409 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T31 |
1 |
| false |
125 |
1 |
|
T30 |
1 |
|
T67 |
1 |
|
T39 |
3 |
| true |
3126 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9877 |
1 |
|
T11 |
1 |
|
T24 |
197 |
|
T76 |
1 |
| others[1] |
444 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T64 |
2 |
| others[2] |
455 |
1 |
|
T63 |
1 |
|
T64 |
6 |
|
T12 |
1 |
| others[3] |
773 |
1 |
|
T11 |
1 |
|
T14 |
1 |
|
T63 |
2 |
| false |
238 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T80 |
1 |
| true |
2034 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9628 |
1 |
|
T11 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
266 |
1 |
|
T39 |
12 |
|
T128 |
2 |
|
T129 |
7 |
| others[2] |
260 |
1 |
|
T30 |
1 |
|
T80 |
1 |
|
T39 |
4 |
| others[3] |
419 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T78 |
1 |
| false |
135 |
1 |
|
T9 |
1 |
|
T39 |
6 |
|
T128 |
1 |
| true |
3113 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9620 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T68 |
1 |
| others[1] |
249 |
1 |
|
T78 |
1 |
|
T39 |
8 |
|
T192 |
1 |
| others[2] |
267 |
1 |
|
T17 |
1 |
|
T9 |
1 |
|
T354 |
1 |
| others[3] |
391 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T80 |
1 |
| false |
128 |
1 |
|
T8 |
1 |
|
T67 |
1 |
|
T39 |
7 |
| true |
3166 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10170 |
1 |
|
T11 |
1 |
|
T24 |
197 |
|
T76 |
1 |
| others[1] |
785 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T63 |
1 |
| others[2] |
781 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T63 |
2 |
| others[3] |
1301 |
1 |
|
T2 |
1 |
|
T63 |
1 |
|
T64 |
9 |
| false |
412 |
1 |
|
T63 |
1 |
|
T64 |
2 |
|
T80 |
1 |
| true |
372 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10182 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T24 |
197 |
| others[1] |
783 |
1 |
|
T63 |
2 |
|
T64 |
10 |
|
T12 |
1 |
| others[2] |
761 |
1 |
|
T63 |
2 |
|
T64 |
3 |
|
T10 |
1 |
| others[3] |
1307 |
1 |
|
T63 |
3 |
|
T64 |
12 |
|
T9 |
1 |
| false |
383 |
1 |
|
T64 |
2 |
|
T67 |
1 |
|
T39 |
8 |
| true |
405 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2399 |
1 |
|
T24 |
43 |
|
T63 |
1 |
|
T64 |
7 |
| others[1] |
2401 |
1 |
|
T24 |
37 |
|
T18 |
1 |
|
T64 |
7 |
| others[2] |
2344 |
1 |
|
T24 |
35 |
|
T25 |
1 |
|
T8 |
1 |
| others[3] |
3984 |
1 |
|
T5 |
1 |
|
T11 |
2 |
|
T24 |
66 |
| false |
1230 |
1 |
|
T24 |
16 |
|
T63 |
3 |
|
T64 |
1 |
| true |
1463 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9682 |
1 |
|
T17 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
264 |
1 |
|
T6 |
1 |
|
T39 |
8 |
|
T129 |
8 |
| others[2] |
264 |
1 |
|
T31 |
1 |
|
T354 |
1 |
|
T39 |
10 |
| others[3] |
438 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T39 |
20 |
| false |
144 |
1 |
|
T39 |
7 |
|
T192 |
1 |
|
T128 |
1 |
| true |
3029 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9847 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T64 |
1 |
| others[1] |
429 |
1 |
|
T11 |
2 |
|
T17 |
1 |
|
T64 |
1 |
| others[2] |
424 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T64 |
5 |
| others[3] |
718 |
1 |
|
T76 |
1 |
|
T64 |
8 |
|
T67 |
2 |
| false |
218 |
1 |
|
T31 |
1 |
|
T63 |
1 |
|
T64 |
1 |
| true |
2185 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9662 |
1 |
|
T6 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
217 |
1 |
|
T17 |
1 |
|
T9 |
1 |
|
T80 |
1 |
| others[2] |
246 |
1 |
|
T30 |
1 |
|
T12 |
1 |
|
T39 |
11 |
| others[3] |
446 |
1 |
|
T11 |
1 |
|
T78 |
1 |
|
T39 |
25 |
| false |
116 |
1 |
|
T67 |
2 |
|
T39 |
1 |
|
T129 |
6 |
| true |
3134 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9631 |
1 |
|
T11 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
232 |
1 |
|
T31 |
1 |
|
T10 |
1 |
|
T39 |
11 |
| others[2] |
228 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T30 |
1 |
| others[3] |
404 |
1 |
|
T17 |
1 |
|
T354 |
1 |
|
T39 |
20 |
| false |
137 |
1 |
|
T6 |
1 |
|
T39 |
3 |
|
T128 |
1 |
| true |
3189 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10138 |
1 |
|
T11 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
766 |
1 |
|
T63 |
2 |
|
T64 |
11 |
|
T39 |
12 |
| others[2] |
808 |
1 |
|
T63 |
1 |
|
T64 |
6 |
|
T354 |
1 |
| others[3] |
1303 |
1 |
|
T8 |
1 |
|
T63 |
2 |
|
T64 |
8 |
| false |
408 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T63 |
1 |
| true |
398 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10167 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T63 |
1 |
| others[1] |
783 |
1 |
|
T63 |
1 |
|
T64 |
10 |
|
T67 |
1 |
| others[2] |
788 |
1 |
|
T63 |
2 |
|
T64 |
9 |
|
T9 |
1 |
| others[3] |
1261 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T11 |
1 |
| false |
410 |
1 |
|
T63 |
1 |
|
T64 |
3 |
|
T39 |
6 |
| true |
412 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2417 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T24 |
34 |
| others[1] |
2439 |
1 |
|
T11 |
1 |
|
T24 |
40 |
|
T63 |
2 |
| others[2] |
2337 |
1 |
|
T24 |
39 |
|
T18 |
1 |
|
T31 |
1 |
| others[3] |
3929 |
1 |
|
T24 |
58 |
|
T8 |
1 |
|
T63 |
1 |
| false |
1291 |
1 |
|
T11 |
1 |
|
T24 |
26 |
|
T63 |
1 |
| true |
1408 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9661 |
1 |
|
T17 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
249 |
1 |
|
T14 |
1 |
|
T9 |
1 |
|
T39 |
15 |
| others[2] |
261 |
1 |
|
T39 |
18 |
|
T128 |
1 |
|
T129 |
11 |
| others[3] |
463 |
1 |
|
T78 |
1 |
|
T80 |
1 |
|
T39 |
18 |
| false |
122 |
1 |
|
T18 |
1 |
|
T10 |
1 |
|
T39 |
3 |
| true |
3065 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9808 |
1 |
|
T11 |
1 |
|
T24 |
197 |
|
T76 |
1 |
| others[1] |
470 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T64 |
3 |
| others[2] |
419 |
1 |
|
T14 |
1 |
|
T64 |
5 |
|
T10 |
1 |
| others[3] |
714 |
1 |
|
T22 |
1 |
|
T30 |
1 |
|
T63 |
4 |
| false |
245 |
1 |
|
T78 |
1 |
|
T64 |
1 |
|
T80 |
1 |
| true |
2165 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9656 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T18 |
1 |
| others[1] |
265 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T14 |
1 |
| others[2] |
262 |
1 |
|
T6 |
1 |
|
T67 |
1 |
|
T10 |
1 |
| others[3] |
423 |
1 |
|
T39 |
15 |
|
T15 |
1 |
|
T129 |
23 |
| false |
112 |
1 |
|
T67 |
1 |
|
T39 |
7 |
|
T192 |
1 |
| true |
3103 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9658 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T24 |
197 |
| others[1] |
228 |
1 |
|
T17 |
1 |
|
T30 |
1 |
|
T39 |
15 |
| others[2] |
238 |
1 |
|
T18 |
1 |
|
T10 |
1 |
|
T39 |
11 |
| others[3] |
426 |
1 |
|
T78 |
1 |
|
T9 |
1 |
|
T39 |
15 |
| false |
122 |
1 |
|
T39 |
6 |
|
T128 |
1 |
|
T129 |
5 |
| true |
3149 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10165 |
1 |
|
T11 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
769 |
1 |
|
T6 |
1 |
|
T30 |
1 |
|
T64 |
3 |
| others[2] |
784 |
1 |
|
T5 |
1 |
|
T64 |
7 |
|
T12 |
1 |
| others[3] |
1309 |
1 |
|
T63 |
4 |
|
T64 |
15 |
|
T354 |
1 |
| false |
398 |
1 |
|
T63 |
1 |
|
T64 |
3 |
|
T67 |
1 |
| true |
396 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10142 |
1 |
|
T11 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
803 |
1 |
|
T17 |
1 |
|
T63 |
4 |
|
T64 |
3 |
| others[2] |
770 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T11 |
1 |
| others[3] |
1291 |
1 |
|
T64 |
17 |
|
T354 |
1 |
|
T39 |
36 |
| false |
403 |
1 |
|
T64 |
4 |
|
T39 |
12 |
|
T120 |
2 |
| true |
412 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2421 |
1 |
|
T24 |
45 |
|
T25 |
1 |
|
T78 |
1 |
| others[1] |
2382 |
1 |
|
T11 |
2 |
|
T24 |
40 |
|
T63 |
1 |
| others[2] |
2403 |
1 |
|
T5 |
1 |
|
T24 |
33 |
|
T63 |
3 |
| others[3] |
3924 |
1 |
|
T24 |
56 |
|
T8 |
1 |
|
T30 |
1 |
| false |
1301 |
1 |
|
T24 |
23 |
|
T64 |
3 |
|
T39 |
9 |
| true |
1390 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9649 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T18 |
1 |
| others[1] |
244 |
1 |
|
T9 |
1 |
|
T80 |
2 |
|
T39 |
7 |
| others[2] |
255 |
1 |
|
T11 |
1 |
|
T78 |
1 |
|
T31 |
1 |
| others[3] |
438 |
1 |
|
T6 |
1 |
|
T13 |
1 |
|
T354 |
1 |
| false |
129 |
1 |
|
T11 |
1 |
|
T39 |
4 |
|
T129 |
4 |
| true |
3106 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |