Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9819 |
1 |
|
T11 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
419 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T11 |
1 |
| others[2] |
417 |
1 |
|
T63 |
2 |
|
T64 |
2 |
|
T67 |
1 |
| others[3] |
793 |
1 |
|
T22 |
1 |
|
T8 |
1 |
|
T63 |
2 |
| false |
237 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T39 |
4 |
| true |
2136 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9646 |
1 |
|
T6 |
1 |
|
T11 |
2 |
|
T24 |
197 |
| others[1] |
256 |
1 |
|
T14 |
1 |
|
T39 |
7 |
|
T191 |
1 |
| others[2] |
249 |
1 |
|
T9 |
1 |
|
T39 |
4 |
|
T128 |
2 |
| others[3] |
385 |
1 |
|
T18 |
1 |
|
T67 |
1 |
|
T13 |
1 |
| false |
131 |
1 |
|
T39 |
7 |
|
T129 |
9 |
|
T142 |
6 |
| true |
3154 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9630 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T78 |
1 |
| others[1] |
249 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T18 |
1 |
| others[2] |
271 |
1 |
|
T11 |
1 |
|
T39 |
7 |
|
T128 |
1 |
| others[3] |
395 |
1 |
|
T8 |
1 |
|
T80 |
1 |
|
T39 |
18 |
| false |
129 |
1 |
|
T17 |
1 |
|
T67 |
1 |
|
T39 |
3 |
| true |
3147 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10197 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T24 |
197 |
| others[1] |
777 |
1 |
|
T63 |
1 |
|
T64 |
8 |
|
T10 |
1 |
| others[2] |
771 |
1 |
|
T22 |
1 |
|
T63 |
2 |
|
T64 |
5 |
| others[3] |
1232 |
1 |
|
T63 |
1 |
|
T64 |
13 |
|
T9 |
1 |
| false |
443 |
1 |
|
T63 |
1 |
|
T64 |
2 |
|
T39 |
13 |
| true |
401 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10158 |
1 |
|
T5 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
819 |
1 |
|
T64 |
6 |
|
T10 |
1 |
|
T39 |
19 |
| others[2] |
749 |
1 |
|
T11 |
1 |
|
T63 |
1 |
|
T64 |
8 |
| others[3] |
1285 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T8 |
1 |
| false |
401 |
1 |
|
T30 |
1 |
|
T64 |
5 |
|
T354 |
1 |
| true |
409 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2357 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T24 |
29 |
| others[1] |
2316 |
1 |
|
T24 |
25 |
|
T25 |
1 |
|
T18 |
1 |
| others[2] |
2472 |
1 |
|
T24 |
48 |
|
T30 |
1 |
|
T64 |
4 |
| others[3] |
4013 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T24 |
75 |
| false |
1201 |
1 |
|
T24 |
20 |
|
T8 |
1 |
|
T63 |
1 |
| true |
1462 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9642 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T68 |
1 |
| others[1] |
242 |
1 |
|
T18 |
1 |
|
T39 |
11 |
|
T15 |
1 |
| others[2] |
242 |
1 |
|
T39 |
7 |
|
T128 |
2 |
|
T129 |
9 |
| others[3] |
486 |
1 |
|
T30 |
1 |
|
T80 |
1 |
|
T12 |
1 |
| false |
147 |
1 |
|
T11 |
1 |
|
T67 |
1 |
|
T354 |
1 |
| true |
3062 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9864 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T63 |
1 |
| others[1] |
403 |
1 |
|
T11 |
1 |
|
T18 |
1 |
|
T64 |
4 |
| others[2] |
437 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T11 |
1 |
| others[3] |
763 |
1 |
|
T64 |
9 |
|
T67 |
1 |
|
T39 |
20 |
| false |
202 |
1 |
|
T78 |
1 |
|
T63 |
1 |
|
T64 |
3 |
| true |
2152 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9653 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T8 |
1 |
| others[1] |
264 |
1 |
|
T6 |
1 |
|
T67 |
1 |
|
T13 |
1 |
| others[2] |
261 |
1 |
|
T11 |
1 |
|
T80 |
1 |
|
T39 |
9 |
| others[3] |
383 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T14 |
1 |
| false |
130 |
1 |
|
T67 |
1 |
|
T39 |
6 |
|
T129 |
8 |
| true |
3130 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9628 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T8 |
1 |
| others[1] |
245 |
1 |
|
T80 |
1 |
|
T354 |
1 |
|
T39 |
14 |
| others[2] |
254 |
1 |
|
T39 |
6 |
|
T128 |
1 |
|
T129 |
21 |
| others[3] |
410 |
1 |
|
T6 |
1 |
|
T39 |
16 |
|
T192 |
1 |
| false |
113 |
1 |
|
T11 |
1 |
|
T39 |
6 |
|
T128 |
1 |
| true |
3171 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10157 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T63 |
2 |
| others[1] |
798 |
1 |
|
T63 |
2 |
|
T64 |
9 |
|
T10 |
1 |
| others[2] |
811 |
1 |
|
T8 |
1 |
|
T63 |
1 |
|
T64 |
11 |
| others[3] |
1251 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T11 |
1 |
| false |
434 |
1 |
|
T64 |
1 |
|
T39 |
12 |
|
T120 |
1 |
| true |
370 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10158 |
1 |
|
T6 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
758 |
1 |
|
T63 |
2 |
|
T64 |
3 |
|
T80 |
1 |
| others[2] |
785 |
1 |
|
T8 |
1 |
|
T64 |
5 |
|
T39 |
19 |
| others[3] |
1311 |
1 |
|
T2 |
1 |
|
T63 |
2 |
|
T64 |
16 |
| false |
413 |
1 |
|
T5 |
1 |
|
T63 |
1 |
|
T64 |
4 |
| true |
396 |
1 |
|
T4 |
1 |
|
T11 |
2 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2361 |
1 |
|
T6 |
1 |
|
T24 |
43 |
|
T25 |
1 |
| others[1] |
2375 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T24 |
37 |
| others[2] |
2399 |
1 |
|
T24 |
31 |
|
T63 |
1 |
|
T64 |
7 |
| others[3] |
4008 |
1 |
|
T11 |
1 |
|
T24 |
68 |
|
T30 |
1 |
| false |
1234 |
1 |
|
T24 |
18 |
|
T63 |
1 |
|
T64 |
3 |
| true |
1444 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9650 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T68 |
1 |
| others[1] |
264 |
1 |
|
T8 |
1 |
|
T30 |
1 |
|
T31 |
1 |
| others[2] |
232 |
1 |
|
T6 |
1 |
|
T14 |
1 |
|
T39 |
7 |
| others[3] |
445 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T39 |
16 |
| false |
118 |
1 |
|
T11 |
1 |
|
T78 |
1 |
|
T39 |
3 |
| true |
3112 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9852 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T18 |
1 |
| others[1] |
442 |
1 |
|
T76 |
1 |
|
T30 |
1 |
|
T64 |
7 |
| others[2] |
470 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T63 |
1 |
| others[3] |
760 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T17 |
1 |
| false |
233 |
1 |
|
T11 |
1 |
|
T64 |
3 |
|
T39 |
14 |
| true |
2064 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9638 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T68 |
1 |
| others[1] |
267 |
1 |
|
T78 |
1 |
|
T14 |
1 |
|
T80 |
1 |
| others[2] |
230 |
1 |
|
T9 |
1 |
|
T13 |
1 |
|
T39 |
8 |
| others[3] |
430 |
1 |
|
T11 |
1 |
|
T30 |
1 |
|
T67 |
1 |
| false |
140 |
1 |
|
T39 |
9 |
|
T128 |
1 |
|
T129 |
8 |
| true |
3116 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9641 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T68 |
1 |
| others[1] |
240 |
1 |
|
T6 |
1 |
|
T39 |
11 |
|
T129 |
6 |
| others[2] |
218 |
1 |
|
T30 |
1 |
|
T9 |
1 |
|
T39 |
7 |
| others[3] |
414 |
1 |
|
T78 |
1 |
|
T39 |
15 |
|
T128 |
2 |
| false |
102 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T10 |
1 |
| true |
3206 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10209 |
1 |
|
T5 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
757 |
1 |
|
T63 |
2 |
|
T64 |
9 |
|
T67 |
1 |
| others[2] |
738 |
1 |
|
T6 |
1 |
|
T11 |
1 |
|
T64 |
6 |
| others[3] |
1319 |
1 |
|
T8 |
1 |
|
T63 |
2 |
|
T64 |
8 |
| false |
404 |
1 |
|
T39 |
8 |
|
T120 |
1 |
|
T81 |
4 |
| true |
394 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10175 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T8 |
1 |
| others[1] |
782 |
1 |
|
T64 |
6 |
|
T9 |
1 |
|
T12 |
1 |
| others[2] |
730 |
1 |
|
T63 |
1 |
|
T64 |
7 |
|
T39 |
12 |
| others[3] |
1347 |
1 |
|
T11 |
1 |
|
T76 |
1 |
|
T63 |
5 |
| false |
406 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T64 |
2 |
| true |
381 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2352 |
1 |
|
T24 |
37 |
|
T63 |
1 |
|
T64 |
5 |
| others[1] |
2419 |
1 |
|
T24 |
36 |
|
T8 |
1 |
|
T63 |
3 |
| others[2] |
2439 |
1 |
|
T24 |
44 |
|
T25 |
1 |
|
T30 |
1 |
| others[3] |
3960 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T11 |
1 |
| false |
1230 |
1 |
|
T11 |
1 |
|
T24 |
17 |
|
T64 |
3 |
| true |
1421 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9638 |
1 |
|
T11 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
249 |
1 |
|
T67 |
1 |
|
T39 |
12 |
|
T129 |
11 |
| others[2] |
273 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T78 |
1 |
| others[3] |
458 |
1 |
|
T67 |
1 |
|
T39 |
14 |
|
T192 |
1 |
| false |
133 |
1 |
|
T18 |
1 |
|
T12 |
1 |
|
T39 |
3 |
| true |
3070 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9818 |
1 |
|
T6 |
1 |
|
T24 |
197 |
|
T25 |
1 |
| others[1] |
443 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T63 |
1 |
| others[2] |
446 |
1 |
|
T11 |
1 |
|
T56 |
1 |
|
T30 |
1 |
| others[3] |
814 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T76 |
1 |
| false |
262 |
1 |
|
T17 |
1 |
|
T63 |
1 |
|
T64 |
2 |
| true |
2038 |
1 |
|
T2 |
1 |
|
T22 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9670 |
1 |
|
T11 |
1 |
|
T17 |
1 |
|
T24 |
197 |
| others[1] |
260 |
1 |
|
T78 |
1 |
|
T31 |
1 |
|
T39 |
10 |
| others[2] |
238 |
1 |
|
T8 |
1 |
|
T10 |
1 |
|
T39 |
13 |
| others[3] |
433 |
1 |
|
T6 |
1 |
|
T39 |
11 |
|
T128 |
2 |
| false |
116 |
1 |
|
T11 |
1 |
|
T13 |
1 |
|
T39 |
6 |
| true |
3104 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9609 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T9 |
1 |
| others[1] |
264 |
1 |
|
T67 |
1 |
|
T39 |
6 |
|
T128 |
1 |
| others[2] |
272 |
1 |
|
T6 |
1 |
|
T11 |
2 |
|
T39 |
12 |
| others[3] |
407 |
1 |
|
T31 |
1 |
|
T80 |
1 |
|
T39 |
25 |
| false |
111 |
1 |
|
T30 |
1 |
|
T39 |
5 |
|
T128 |
1 |
| true |
3158 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10220 |
1 |
|
T24 |
197 |
|
T25 |
1 |
|
T63 |
2 |
| others[1] |
760 |
1 |
|
T11 |
1 |
|
T8 |
1 |
|
T63 |
1 |
| others[2] |
780 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T63 |
1 |
| others[3] |
1299 |
1 |
|
T6 |
1 |
|
T22 |
1 |
|
T63 |
2 |
| false |
378 |
1 |
|
T11 |
1 |
|
T76 |
1 |
|
T63 |
1 |
| true |
384 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T56 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |