Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	194714	1		T2	1645		T6	161		T5	44
auto[FlashEraseBank]	219163	1		T2	1273		T6	39		T5	20

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	231989	1		T2	1164		T6	83		T5	35
auto[FlashOpProgram]	162242	1		T2	1754		T6	72		T5	15
auto[FlashOpErase]	15646	1		T6	45		T5	14		T7	10
auto[FlashOpInvalid]	4000	1		T141	200		T301	200		T143	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	231989	1		T2	1164		T6	83		T5	35
op[FlashOpProgram]	162242	1		T2	1754		T6	72		T5	15
op[FlashOpErase]	15646	1		T6	45		T5	14		T7	10
read_erase_read	768	1		T6	10		T5	5		T7	1
read_prog_read	527	1		T2	4		T6	13		T5	4

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	288656	1		T2	2328		T6	198		T5	61
auto[FlashPartInfo]	122272	1		T2	575		T6	1		T5	3
auto[FlashPartInfo1]	771	1		T2	1		T17	3		T25	64
auto[FlashPartInfo2]	2178	1		T2	14		T6	1		T17	9

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	167122	1		T2	838		T6	82		T5	32
auto[FlashPartData]	auto[FlashOpProgram]	113949	1		T2	1490		T6	72		T5	15
auto[FlashPartData]	auto[FlashOpErase]	3681	1		T6	44		T5	14		T63	1
auto[FlashPartData]	auto[FlashOpInvalid]	3904	1		T141	198		T301	200		T143	194
auto[FlashPartInfo]	auto[FlashOpRead]	62731	1		T2	321		T5	3		T7	14
auto[FlashPartInfo]	auto[FlashOpProgram]	47511	1		T2	254		T7	192		T24	297
auto[FlashPartInfo]	auto[FlashOpErase]	11938	1		T6	1		T7	10		T24	297
auto[FlashPartInfo]	auto[FlashOpInvalid]	92	1		T141	2		T143	6		T339	2
auto[FlashPartInfo1]	auto[FlashOpRead]	610	1		T2	1		T17	3		T25	32
auto[FlashPartInfo1]	auto[FlashOpProgram]	160	1		T25	32		T68	32		T149	32
auto[FlashPartInfo1]	auto[FlashOpErase]	1	1		T131	1		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1526	1		T2	4		T6	1		T17	9
auto[FlashPartInfo2]	auto[FlashOpProgram]	622	1		T2	10		T25	64		T30	7
auto[FlashPartInfo2]	auto[FlashOpErase]	26	1		T128	2		T151	1		T152	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T152	2		T340	2		-	-