Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.57	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	9	23	71.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	9	23	71.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30363	1		T6	40		T5	8		T7	4
auto[1]	4	1		T313	1		T314	3		-	-
auto[2]	32	1		T73	4		T153	4		T154	8
auto[3]	44	1		T12	2		T13	2		T127	2

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7608	1		T6	10		T5	2		T7	1
evic_idx[1]	7608	1		T6	10		T5	2		T7	1
evic_idx[2]	7614	1		T6	10		T5	2		T7	1
evic_idx[3]	7613	1		T6	10		T5	2		T7	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29472	1		T7	4		T24	612		T65	4
evic_op[2]	287	1		T12	2		T13	2		T120	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	9	23	71.88	9

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0] , evic_idx[1] , evic_idx[2]]	[evic_op[1]]	[auto[1]]	--	--	3
[evic_idx[0] , evic_idx[1] , evic_idx[2]]	[evic_op[2]]	[auto[2]]	--	--	3
[evic_idx[3]]	[evic_op[1]]	[auto[1]]	0	1	1
[evic_idx[3]]	[evic_op[2]]	[auto[1] - auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7363	1		T7	1		T24	153		T65	1
evic_idx[0]	evic_op[1]	auto[2]	1	1		T73	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	4	1		T315	2		T316	1		T317	1
evic_idx[0]	evic_op[2]	auto[0]	64	1		T129	1		T142	2		T175	7
evic_idx[0]	evic_op[2]	auto[1]	1	1		T314	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	4	1		T127	1		T318	2		T72	1
evic_idx[1]	evic_op[1]	auto[0]	7360	1		T7	1		T24	153		T65	1
evic_idx[1]	evic_op[1]	auto[2]	1	1		T73	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	6	1		T319	1		T315	2		T316	1
evic_idx[1]	evic_op[2]	auto[0]	65	1		T129	1		T142	2		T175	7
evic_idx[1]	evic_op[2]	auto[1]	1	1		T314	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	4	1		T13	1		T318	1		T72	1
evic_idx[2]	evic_op[1]	auto[0]	7359	1		T7	1		T24	153		T65	1
evic_idx[2]	evic_op[1]	auto[2]	1	1		T73	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	7	1		T320	1		T319	1		T315	2
evic_idx[2]	evic_op[2]	auto[0]	67	1		T129	1		T142	2		T175	7
evic_idx[2]	evic_op[2]	auto[1]	2	1		T313	1		T314	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	7	1		T12	1		T13	1		T140	1
evic_idx[3]	evic_op[1]	auto[0]	7361	1		T7	1		T24	153		T65	1
evic_idx[3]	evic_op[1]	auto[2]	1	1		T73	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	8	1		T320	1		T319	1		T315	2
evic_idx[3]	evic_op[2]	auto[0]	68	1		T120	1		T129	1		T142	2
evic_idx[3]	evic_op[2]	auto[3]	4	1		T12	1		T127	1		T318	1