Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	31263	1		T121	2504		T326	7911		T327	8792
rd_lvl[2]	38987	1		T121	1813		T328	1609		T326	3641
rd_lvl[3]	11287	1		T121	672		T328	1308		T329	446
rd_lvl[4]	26242	1		T14	3067		T121	890		T330	2627
rd_lvl[5]	15693	1		T14	1210		T121	566		T331	1700
rd_lvl[6]	10050	1		T121	106		T332	965		T331	757
rd_lvl[7]	10539	1		T121	499		T332	443		T331	48
rd_lvl[8]	13057	1		T121	533		T331	31		T333	1389
rd_lvl[9]	8005	1		T121	864		T75	200		T334	667
rd_lvl[10]	6245	1		T121	171		T75	811		T334	395
rd_lvl[11]	6306	1		T121	216		T331	32		T335	945
rd_lvl[12]	7423	1		T15	504		T121	1		T75	88
rd_lvl[13]	6723	1		T15	227		T336	238		T174	233
rd_lvl[14]	4741	1		T74	526		T180	403		T121	52
rd_lvl[15]	5361	1		T16	471		T74	291		T180	334