Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	293116	1		T1	1		T2	2		T3	1
all_pins[1]	293116	1		T1	1		T2	2		T3	1
all_pins[2]	293116	1		T1	1		T2	2		T3	1
all_pins[3]	293116	1		T1	1		T2	2		T3	1
all_pins[4]	293116	1		T1	1		T2	2		T3	1
all_pins[5]	293116	1		T1	1		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1466378	1		T1	6		T2	12		T3	6
values[0x1]	292318	1		T14	5371		T15	1462		T16	3074
transitions[0x0=>0x1]	262776	1		T14	4340		T15	1462		T16	2006
transitions[0x1=>0x0]	262760	1		T14	4340		T15	1462		T16	2006

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	292971	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	145	1		T265	4		T266	6		T323	1
all_pins[0]	transitions[0x0=>0x1]	69	1		T266	3		T321	1		T324	1
all_pins[0]	transitions[0x1=>0x0]	90	1		T264	1		T265	2		T323	4
all_pins[1]	values[0x0]	292950	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	166	1		T264	1		T265	6		T266	3
all_pins[1]	transitions[0x0=>0x1]	138	1		T264	1		T265	4		T266	3
all_pins[1]	transitions[0x1=>0x0]	3519	1		T16	534		T74	2		T294	118
all_pins[2]	values[0x0]	289569	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	3547	1		T16	534		T74	2		T294	118
all_pins[2]	transitions[0x0=>0x1]	40	1		T264	1		T265	1		T266	1
all_pins[2]	transitions[0x1=>0x0]	202757	1		T14	4277		T15	731		T16	471
all_pins[3]	values[0x0]	86852	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	206264	1		T14	4277		T15	731		T16	1005
all_pins[3]	transitions[0x0=>0x1]	180371	1		T14	3246		T15	731		T16	471
all_pins[3]	transitions[0x1=>0x0]	56247	1		T14	63		T15	731		T16	1001
all_pins[4]	values[0x0]	210976	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	82140	1		T14	1094		T15	731		T16	1535
all_pins[4]	transitions[0x0=>0x1]	82135	1		T14	1094		T15	731		T16	1535
all_pins[4]	transitions[0x1=>0x0]	51	1		T264	1		T265	3		T323	2
all_pins[5]	values[0x0]	293060	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	56	1		T264	1		T265	3		T323	3
all_pins[5]	transitions[0x0=>0x1]	23	1		T265	2		T323	1		T321	1
all_pins[5]	transitions[0x1=>0x0]	96	1		T265	2		T266	5		T321	2