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 LINE       11938
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T6
11CoveredT1,T2,T3

 LINE       11938
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T22,T47
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T22,T47
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T25
11CoveredT17,T22,T76

 LINE       11938
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T22
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T25,T64
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T56
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T5
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T5
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T25,T9
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T25
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T22,T47
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T22,T76
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T22,T47
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T56
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T25
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T25,T89
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T47
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T56
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T47,T76

 LINE       11938
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T56
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T76
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T56
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T56
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T76,T25
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T25,T92
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T22,T47
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T56
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T56
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T22
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T47,T76

 LINE       11938
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T22
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T22
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T25
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T47
11CoveredT17,T25,T8

 LINE       11938
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T25
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T47
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T22
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T22,T56
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T25
11CoveredT17,T47,T76

 LINE       11938
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T25,T8
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T47
11CoveredT17,T76,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T47
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T76
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[73] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[74] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[75] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[76] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[77] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[78] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[79] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[80] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[81] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[82] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T47,T76

 LINE       11938
 SUB-EXPRESSION (addr_hit[83] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T56
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[84] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[85] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T25
11CoveredT3,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[86] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T76,T25
11CoveredT17,T22,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[87] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[88] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T4
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[89] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T17
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[90] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T47
11CoveredT17,T47,T76

 LINE       11938
 SUB-EXPRESSION (addr_hit[91] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T5,T11
11CoveredT17,T47,T76

 LINE       11938
 SUB-EXPRESSION (addr_hit[92] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T5

 LINE       11938
 SUB-EXPRESSION (addr_hit[93] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[94] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T22,T25
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[95] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T17,T22
11CoveredT4,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[96] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T56
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[97] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T25
11CoveredT4,T17,T22

 LINE       11938
 SUB-EXPRESSION (addr_hit[98] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T25
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[99] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T22,T47
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[100] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T56,T25
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[101] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T25,T15
11CoveredT17,T47,T76

 LINE       11938
 SUB-EXPRESSION (addr_hit[102] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T22,T47
11CoveredT17,T47,T25

 LINE       11938
 SUB-EXPRESSION (addr_hit[103] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T25,T92
11CoveredT17,T22,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[104] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T25,T15
11CoveredT3,T17,T47

 LINE       11938
 SUB-EXPRESSION (addr_hit[105] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T25
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[106] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T47,T76
11CoveredT17,T47,T56

 LINE       11938
 SUB-EXPRESSION (addr_hit[107] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T47
11CoveredT17,T47,T56

 LINE       12050
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT189,T201,T262
111CoveredT2,T6,T7

 LINE       12055
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T22,T47
110CoveredT189,T201,T263
111CoveredT14,T12,T13

 LINE       12068
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T22,T47
110CoveredT188,T263,T262
111CoveredT264,T265,T266

 LINE       12081
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T22,T47
110CoveredT188,T189,T267
111CoveredT8,T9,T10

 LINE       12092
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T17,T22
110CoveredT189,T201,T268
111CoveredT22,T23,T48

 LINE       12095
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T47,T56
110CoveredT188,T201,T262
111CoveredT64,T81,T82

 LINE       12098
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T6,T4
101CoveredT1,T2,T3
110CoveredT201,T263,T269
111CoveredT1,T2,T3

 LINE       12101
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T47,T56
110CoveredT207
111CoveredT59,T199,T200

 LINE       12102
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T6,T5
110CoveredT189,T201,T270
111CoveredT2,T6,T5

 LINE       12117
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T6,T5
110CoveredT263,T271,T272
111CoveredT2,T6,T5

 LINE       12120
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T47,T25
110CoveredT189,T201,T267
111CoveredT32,T33,T34

 LINE       12125
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T22,T47
110CoveredT189,T201,T263
111CoveredT153,T40,T41

 LINE       12128
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T22,T47
110CoveredT201,T271,T270
111CoveredT122,T57,T58

 LINE       12131
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T22,T47
110CoveredT189,T201,T272
111CoveredT122,T57,T58

 LINE       12134
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T17,T22
110CoveredT201,T273,T269
111CoveredT122,T57,T58

 LINE       12137
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T47,T56
110CoveredT189,T201,T274
111CoveredT122,T57,T58

 LINE       12140
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T17,T47
110CoveredT201,T263,T269
111CoveredT122,T57,T58

 LINE       12143
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T47,T56
110CoveredT189,T201,T269
111CoveredT122,T57,T58

 LINE       12146
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T17,T22
110CoveredT189,T263,T275
111CoveredT122,T57,T58

 LINE       12149
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T22,T47
110CoveredT188,T263,T262
111CoveredT122,T57,T58

 LINE       12152
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T6
110CoveredT189,T201,T262
111CoveredT2,T6,T4

 LINE       12167
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T6
110CoveredT188,T189,T201
111CoveredT2,T6,T4

 LINE       12182
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T6,T4
110CoveredT188,T201,T262
111CoveredT2,T6,T4

 LINE       12197
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T6,T4
110CoveredT188,T189,T201
111CoveredT2,T6,T4

 LINE       12212
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T6,T4
110CoveredT189,T201,T269
111CoveredT2,T6,T4

 LINE       12227
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T6,T4
110CoveredT189,T201,T262
111CoveredT2,T6,T4

 LINE       12242
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T6
110CoveredT189,T201,T267
111CoveredT2,T6,T4

 LINE       12257
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T6,T4
110CoveredT188,T189,T263
111CoveredT2,T6,T4

 LINE       12272
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T6,T4
110CoveredT188,T263,T262
111CoveredT2,T6,T4
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%