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 LINE       12277
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T201,T263,T262
1	1	1	Covered	T2,T6,T4

 LINE       12282
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T189,T201,T262
1	1	1	Covered	T2,T6,T4

 LINE       12287
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T201,T263,T269
1	1	1	Covered	T2,T6,T4

 LINE       12292
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T189,T201,T263
1	1	1	Covered	T2,T6,T4

 LINE       12297
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T201,T263,T269
1	1	1	Covered	T2,T6,T4

 LINE       12302
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T189,T263,T269
1	1	1	Covered	T2,T6,T4

 LINE       12307
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T188,T189,T262
1	1	1	Covered	T2,T6,T4

 LINE       12312
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T188,T201,T273
1	1	1	Covered	T2,T6,T4

 LINE       12325
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T47
1	1	0	Covered	T201,T269,T276
1	1	1	Covered	T122,T57,T58

 LINE       12328
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T22,T47
1	1	0	Covered	T263,T271,T270
1	1	1	Covered	T122,T57,T58

 LINE       12331
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T47,T56
1	1	0	Covered	T189,T263,T262
1	1	1	Covered	T122,T57,T58

 LINE       12334
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T47,T56
1	1	0	Covered	T201,T262,T269
1	1	1	Covered	T122,T57,T58

 LINE       12337
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T47
1	1	0	Covered	T188,T189,T201
1	1	1	Covered	T57,T58,T59

 LINE       12340
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T47,T56
1	1	0	Covered	T201,T263,T262
1	1	1	Covered	T122,T57,T58

 LINE       12343
 EXPRESSION (addr_hit[43] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T22,T47
1	1	0	Covered	T189,T205,T262
1	1	1	Covered	T122,T57,T58

 LINE       12346
 EXPRESSION (addr_hit[44] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T47,T56
1	1	0	Covered	T189,T201,T269
1	1	1	Covered	T122,T57,T58

 LINE       12349
 EXPRESSION (addr_hit[45] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T22,T47
1	1	0	Covered	T189,T263,T269
1	1	1	Covered	T122,T57,T58

 LINE       12352
 EXPRESSION (addr_hit[46] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T22
1	1	0	Covered	T201,T263,T271
1	1	1	Covered	T122,T57,T58

 LINE       12355
 EXPRESSION (addr_hit[47] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T201,T271,T272
1	1	1	Covered	T2,T6,T4

 LINE       12370
 EXPRESSION (addr_hit[48] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T201,T269,T272
1	1	1	Covered	T2,T6,T4

 LINE       12385
 EXPRESSION (addr_hit[49] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T188,T201,T202
1	1	1	Covered	T2,T6,T4

 LINE       12400
 EXPRESSION (addr_hit[50] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T189,T201,T277
1	1	1	Covered	T2,T6,T4

 LINE       12415
 EXPRESSION (addr_hit[51] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T188,T189,T262
1	1	1	Covered	T2,T6,T4

 LINE       12430
 EXPRESSION (addr_hit[52] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T189,T201,T263
1	1	1	Covered	T2,T6,T4

 LINE       12445
 EXPRESSION (addr_hit[53] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T189,T201,T262
1	1	1	Covered	T2,T6,T4

 LINE       12460
 EXPRESSION (addr_hit[54] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T189,T201,T263
1	1	1	Covered	T2,T6,T4

 LINE       12475
 EXPRESSION (addr_hit[55] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T189,T201,T263
1	1	1	Covered	T2,T6,T4

 LINE       12490
 EXPRESSION (addr_hit[56] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T263,T269,T271
1	1	1	Covered	T2,T6,T4

 LINE       12505
 EXPRESSION (addr_hit[57] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T22
1	1	0	Covered	T188,T201,T269
1	1	1	Covered	T122,T57,T58

 LINE       12508
 EXPRESSION (addr_hit[58] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T263,T269,T270
1	1	1	Covered	T2,T6,T4

 LINE       12523
 EXPRESSION (addr_hit[59] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T22
1	1	0	Covered	T188,T201,T278
1	1	1	Covered	T57,T58,T59

 LINE       12526
 EXPRESSION (addr_hit[60] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T22,T47
1	1	0	Covered	T201,T263,T262
1	1	1	Covered	T122,T57,T58

 LINE       12529
 EXPRESSION (addr_hit[61] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T201,T263,T269
1	1	1	Covered	T2,T6,T4

 LINE       12544
 EXPRESSION (addr_hit[62] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T188,T189,T201
1	1	1	Covered	T2,T6,T4

 LINE       12559
 EXPRESSION (addr_hit[63] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T47
1	1	0	Covered	T201,T269,T271
1	1	1	Covered	T122,T57,T58

 LINE       12562
 EXPRESSION (addr_hit[64] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T47,T25
1	1	0	Covered	T188,T189,T263
1	1	1	Covered	T122,T57,T58

 LINE       12565
 EXPRESSION (addr_hit[65] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T47
1	1	0	Covered	T189,T201,T263
1	1	1	Covered	T122,T57,T58

 LINE       12568
 EXPRESSION (addr_hit[66] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T22
1	1	0	Covered	T201,T263,T269
1	1	1	Covered	T122,T57,T58

 LINE       12571
 EXPRESSION (addr_hit[67] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T22
1	1	0	Covered	T201,T279,T263
1	1	1	Covered	T122,T57,T58

 LINE       12574
 EXPRESSION (addr_hit[68] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T47,T76
1	1	0	Covered	T188,T201,T269
1	1	1	Covered	T122,T57,T58

 LINE       12577
 EXPRESSION (addr_hit[69] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T22,T47
1	1	0	Covered	T263,T269,T280
1	1	1	Covered	T122,T57,T58

 LINE       12580
 EXPRESSION (addr_hit[70] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T47
1	1	0	Covered	T189,T263,T269
1	1	1	Covered	T122,T57,T58

 LINE       12583
 EXPRESSION (addr_hit[71] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T47
1	1	0	Covered	T188,T263,T262
1	1	1	Covered	T122,T57,T58

 LINE       12586
 EXPRESSION (addr_hit[72] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T22,T47
1	1	0	Covered	T189,T201,T263
1	1	1	Covered	T57,T58,T59

 LINE       12589
 EXPRESSION (addr_hit[73] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T188,T189,T201
1	1	1	Covered	T2,T6,T4

 LINE       12604
 EXPRESSION (addr_hit[74] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T188,T189,T201
1	1	1	Covered	T2,T6,T4

 LINE       12619
 EXPRESSION (addr_hit[75] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T188,T189,T201
1	1	1	Covered	T2,T6,T4

 LINE       12634
 EXPRESSION (addr_hit[76] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T189,T201,T263
1	1	1	Covered	T2,T6,T4

 LINE       12649
 EXPRESSION (addr_hit[77] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T263,T262,T271
1	1	1	Covered	T2,T6,T4

 LINE       12664
 EXPRESSION (addr_hit[78] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T188,T189,T281
1	1	1	Covered	T2,T6,T4

 LINE       12679
 EXPRESSION (addr_hit[79] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T201,T263,T269
1	1	1	Covered	T2,T6,T4

 LINE       12694
 EXPRESSION (addr_hit[80] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T189,T201,T263
1	1	1	Covered	T2,T6,T4

 LINE       12709
 EXPRESSION (addr_hit[81] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T188,T262,T270
1	1	1	Covered	T2,T6,T4

 LINE       12724
 EXPRESSION (addr_hit[82] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T188,T189,T201
1	1	1	Covered	T2,T6,T4

 LINE       12739
 EXPRESSION (addr_hit[83] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T22
1	1	0	Covered	T189,T263,T269
1	1	1	Covered	T122,T57,T58

 LINE       12742
 EXPRESSION (addr_hit[84] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T201,T263,T269
1	1	1	Covered	T2,T6,T4

 LINE       12757
 EXPRESSION (addr_hit[85] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T22
1	1	0	Covered	T201,T262,T282
1	1	1	Covered	T122,T57,T58

 LINE       12760
 EXPRESSION (addr_hit[86] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T22,T76
1	1	0	Covered	T188,T189,T201
1	1	1	Covered	T122,T57,T58

 LINE       12763
 EXPRESSION (addr_hit[87] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T279,T263,T262
1	1	1	Covered	T2,T6,T4

 LINE       12778
 EXPRESSION (addr_hit[88] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T4
1	1	0	Covered	T189,T201,T283
1	1	1	Covered	T2,T6,T4

 LINE       12793
 EXPRESSION (addr_hit[89] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T7,T17
1	1	0	Covered	T188,T199,T201
1	1	1	Covered	T7,T65,T86

 LINE       12798
 EXPRESSION (addr_hit[90] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T47
1	1	0	Covered	T189,T263,T270
1	1	1	Covered	T122,T57,T58

 LINE       12801
 EXPRESSION (addr_hit[91] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T5,T11
1	1	0	Not Covered
1	1	1	Covered	T122,T57,T58

 LINE       12802
 EXPRESSION (addr_hit[91] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T5,T11
1	1	0	Covered	T189,T201,T284
1	1	1	Covered	T6,T5,T11

 LINE       12807
 EXPRESSION (addr_hit[92] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T60,T189,T201
1	1	1	Covered	T2,T6,T5

 LINE       12812
 EXPRESSION (addr_hit[94] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T22,T47
1	1	0	Covered	T60,T279
1	1	1	Covered	T96,T97,T98

 LINE       12813
 EXPRESSION (addr_hit[95] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T4,T17
1	1	0	Covered	T188,T189,T201
1	1	1	Covered	T6,T12,T13

 LINE       12830
 EXPRESSION (addr_hit[97] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T17,T22
1	1	0	Covered	T188,T263,T262
1	1	1	Covered	T122,T57,T58

 LINE       12835
 EXPRESSION (addr_hit[99] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T22,T47
1	1	0	Covered	T201,T270,T280
1	1	1	Covered	T122,T57,T58

 LINE       12840
 EXPRESSION (addr_hit[102] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T22
1	1	0	Covered	T189,T201,T262
1	1	1	Not Covered

 LINE       12845
 EXPRESSION (addr_hit[104] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T47
1	1	0	Covered	T205,T262,T269
1	1	1	Covered	T122,T57,T58

 LINE       12848
 EXPRESSION (addr_hit[105] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T47,T56
1	1	0	Covered	T188,T278,T269
1	1	1	Covered	T14,T15,T16

 LINE       12853
 EXPRESSION (addr_hit[106] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T47,T56
1	1	0	Covered	T188,T189,T201
1	1	1	Covered	T122,T57,T58

 LINE       12856
 EXPRESSION (addr_hit[107] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T47
1	1	0	Covered	T207
1	1	1	Covered	T14,T15,T16

 LINE       13717
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T202
1	1	Covered	T1,T2,T3