Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287763	1		T1	2		T2	2		T3	1
all_values[1]	287763	1		T1	2		T2	2		T3	1
all_values[2]	287763	1		T1	2		T2	2		T3	1
all_values[3]	287763	1		T1	2		T2	2		T3	1
all_values[4]	287763	1		T1	2		T2	2		T3	1
all_values[5]	287763	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	581046	1		T1	12		T2	12		T3	6
auto[1]	1145532	1		T5	6560		T14	8220		T15	7752

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	840915	1		T1	7		T2	7		T3	4
auto[1]	885663	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	287610	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	153	1		T256	6		T257	5		T258	6
all_values[1]	auto[0]	auto[1]	287592	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	171	1		T256	2		T257	3		T258	6
all_values[2]	auto[0]	auto[0]	1402	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	59	1		T256	1		T258	2		T296	2
all_values[2]	auto[1]	auto[0]	286250	1		T5	1640		T14	2055		T15	1938
all_values[2]	auto[1]	auto[1]	52	1		T256	1		T257	4		T297	2
all_values[3]	auto[0]	auto[0]	1405	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	65	1		T256	1		T257	2		T297	2
all_values[3]	auto[1]	auto[0]	54219	1		T5	820		T14	1000		T15	969
all_values[3]	auto[1]	auto[1]	232074	1		T5	820		T14	1055		T15	969
all_values[4]	auto[0]	auto[0]	984	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	461	1		T1	1		T2	1		T6	1
all_values[4]	auto[1]	auto[0]	209064	1		T5	820		T14	1000		T15	969
all_values[4]	auto[1]	auto[1]	77254	1		T5	820		T14	1055		T15	969
all_values[5]	auto[0]	auto[0]	1363	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	105	1		T6	1		T42	1		T39	1
all_values[5]	auto[1]	auto[0]	286228	1		T5	1640		T14	2055		T15	1938
all_values[5]	auto[1]	auto[1]	67	1		T256	4		T257	3		T258	1