Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T1 |
6 |
|
T16 |
1 |
|
T4 |
2 |
| others[1] |
224 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T17 |
1 |
| others[2] |
214 |
1 |
|
T1 |
6 |
|
T138 |
7 |
|
T130 |
1 |
| others[3] |
355 |
1 |
|
T1 |
15 |
|
T10 |
1 |
|
T4 |
3 |
| false |
118 |
1 |
|
T1 |
7 |
|
T42 |
1 |
|
T11 |
2 |
| true |
12652 |
1 |
|
T1 |
55 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8214 |
1 |
|
T1 |
20 |
|
T16 |
1 |
|
T4 |
2 |
| others[1] |
1230 |
1 |
|
T1 |
19 |
|
T4 |
3 |
|
T5 |
1 |
| others[2] |
1285 |
1 |
|
T1 |
19 |
|
T10 |
1 |
|
T4 |
5 |
| others[3] |
2106 |
1 |
|
T1 |
33 |
|
T4 |
6 |
|
T12 |
1 |
| false |
627 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T54 |
1 |
| true |
319 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8244 |
1 |
|
T1 |
15 |
|
T4 |
5 |
|
T20 |
2 |
| others[1] |
1290 |
1 |
|
T1 |
22 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
1239 |
1 |
|
T1 |
22 |
|
T10 |
1 |
|
T4 |
2 |
| others[3] |
2060 |
1 |
|
T1 |
33 |
|
T4 |
5 |
|
T12 |
1 |
| false |
652 |
1 |
|
T1 |
9 |
|
T4 |
3 |
|
T93 |
1 |
| true |
296 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T1 |
5 |
|
T4 |
2 |
|
T17 |
1 |
| others[1] |
97 |
1 |
|
T1 |
5 |
|
T10 |
1 |
|
T4 |
2 |
| others[2] |
112 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T138 |
2 |
| others[3] |
180 |
1 |
|
T1 |
5 |
|
T4 |
10 |
|
T138 |
9 |
| false |
60 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T138 |
1 |
| true |
13216 |
1 |
|
T1 |
76 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T1 |
12 |
|
T11 |
1 |
|
T138 |
6 |
| others[1] |
238 |
1 |
|
T1 |
9 |
|
T4 |
3 |
|
T138 |
15 |
| others[2] |
208 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T15 |
1 |
| others[3] |
373 |
1 |
|
T1 |
21 |
|
T4 |
4 |
|
T14 |
1 |
| false |
106 |
1 |
|
T1 |
2 |
|
T6 |
1 |
|
T138 |
2 |
| true |
12614 |
1 |
|
T1 |
45 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8012 |
1 |
|
T1 |
17 |
|
T4 |
2 |
|
T17 |
1 |
| others[1] |
1032 |
1 |
|
T1 |
22 |
|
T6 |
1 |
|
T10 |
1 |
| others[2] |
1031 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T84 |
1 |
| others[3] |
1787 |
1 |
|
T1 |
35 |
|
T3 |
1 |
|
T4 |
9 |
| false |
574 |
1 |
|
T1 |
11 |
|
T83 |
1 |
|
T13 |
1 |
| true |
1345 |
1 |
|
T16 |
1 |
|
T15 |
1 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T1 |
9 |
|
T4 |
3 |
|
T14 |
1 |
| others[1] |
227 |
1 |
|
T1 |
5 |
|
T4 |
5 |
|
T42 |
1 |
| others[2] |
214 |
1 |
|
T1 |
11 |
|
T138 |
8 |
|
T55 |
1 |
| others[3] |
366 |
1 |
|
T1 |
21 |
|
T4 |
2 |
|
T17 |
1 |
| false |
125 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T138 |
7 |
| true |
12604 |
1 |
|
T1 |
50 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T1 |
7 |
|
T16 |
1 |
|
T4 |
2 |
| others[1] |
200 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T11 |
3 |
| others[2] |
229 |
1 |
|
T1 |
11 |
|
T93 |
1 |
|
T138 |
10 |
| others[3] |
366 |
1 |
|
T1 |
17 |
|
T6 |
1 |
|
T10 |
1 |
| false |
110 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T11 |
1 |
| true |
12650 |
1 |
|
T1 |
54 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8208 |
1 |
|
T1 |
18 |
|
T4 |
4 |
|
T15 |
1 |
| others[1] |
1211 |
1 |
|
T1 |
26 |
|
T10 |
1 |
|
T4 |
4 |
| others[2] |
1249 |
1 |
|
T1 |
20 |
|
T4 |
1 |
|
T138 |
16 |
| others[3] |
2151 |
1 |
|
T1 |
30 |
|
T4 |
8 |
|
T13 |
1 |
| false |
644 |
1 |
|
T1 |
7 |
|
T138 |
7 |
|
T30 |
1 |
| true |
318 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1276 |
1 |
|
T1 |
16 |
|
T10 |
1 |
|
T4 |
1 |
| others[1] |
1178 |
1 |
|
T1 |
29 |
|
T4 |
4 |
|
T5 |
1 |
| others[2] |
1281 |
1 |
|
T1 |
15 |
|
T4 |
4 |
|
T12 |
1 |
| others[3] |
2141 |
1 |
|
T1 |
32 |
|
T16 |
1 |
|
T4 |
6 |
| false |
610 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T15 |
1 |
| true |
290 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T1 |
3 |
|
T10 |
1 |
|
T4 |
3 |
| others[1] |
100 |
1 |
|
T1 |
2 |
|
T4 |
4 |
|
T12 |
1 |
| others[2] |
100 |
1 |
|
T1 |
4 |
|
T4 |
3 |
|
T13 |
1 |
| others[3] |
191 |
1 |
|
T1 |
4 |
|
T4 |
5 |
|
T93 |
1 |
| false |
57 |
1 |
|
T1 |
2 |
|
T4 |
2 |
|
T138 |
4 |
| true |
6218 |
1 |
|
T1 |
86 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T1 |
11 |
|
T10 |
1 |
|
T4 |
1 |
| others[1] |
211 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T138 |
10 |
| others[2] |
238 |
1 |
|
T1 |
10 |
|
T4 |
3 |
|
T11 |
1 |
| others[3] |
363 |
1 |
|
T1 |
24 |
|
T4 |
4 |
|
T14 |
1 |
| false |
136 |
1 |
|
T1 |
5 |
|
T6 |
1 |
|
T138 |
7 |
| true |
5612 |
1 |
|
T1 |
40 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1055 |
1 |
|
T1 |
21 |
|
T4 |
5 |
|
T11 |
1 |
| others[1] |
1046 |
1 |
|
T1 |
15 |
|
T3 |
1 |
|
T10 |
1 |
| others[2] |
1070 |
1 |
|
T1 |
21 |
|
T4 |
3 |
|
T138 |
23 |
| others[3] |
1746 |
1 |
|
T1 |
34 |
|
T6 |
1 |
|
T4 |
4 |
| false |
565 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T138 |
15 |
| true |
1294 |
1 |
|
T14 |
1 |
|
T82 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T138 |
10 |
| others[1] |
217 |
1 |
|
T1 |
7 |
|
T10 |
1 |
|
T16 |
1 |
| others[2] |
243 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T15 |
1 |
| others[3] |
365 |
1 |
|
T1 |
18 |
|
T4 |
3 |
|
T84 |
1 |
| false |
101 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T138 |
2 |
| true |
5619 |
1 |
|
T1 |
55 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T1 |
11 |
|
T84 |
1 |
|
T138 |
11 |
| others[1] |
213 |
1 |
|
T1 |
8 |
|
T6 |
1 |
|
T4 |
1 |
| others[2] |
209 |
1 |
|
T1 |
7 |
|
T10 |
1 |
|
T4 |
2 |
| others[3] |
362 |
1 |
|
T1 |
13 |
|
T16 |
1 |
|
T4 |
4 |
| false |
111 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T138 |
7 |
| true |
5675 |
1 |
|
T1 |
59 |
|
T3 |
1 |
|
T4 |
9 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T1 |
25 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
1263 |
1 |
|
T1 |
27 |
|
T4 |
4 |
|
T138 |
17 |
| others[2] |
1235 |
1 |
|
T1 |
16 |
|
T10 |
1 |
|
T16 |
1 |
| others[3] |
2062 |
1 |
|
T1 |
28 |
|
T4 |
8 |
|
T12 |
1 |
| false |
649 |
1 |
|
T1 |
5 |
|
T138 |
12 |
|
T58 |
7 |
| true |
317 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1267 |
1 |
|
T1 |
23 |
|
T54 |
1 |
|
T138 |
14 |
| others[1] |
1253 |
1 |
|
T1 |
17 |
|
T10 |
1 |
|
T4 |
3 |
| others[2] |
1236 |
1 |
|
T1 |
20 |
|
T4 |
5 |
|
T138 |
27 |
| others[3] |
2097 |
1 |
|
T1 |
32 |
|
T4 |
5 |
|
T54 |
1 |
| false |
630 |
1 |
|
T1 |
9 |
|
T4 |
4 |
|
T138 |
13 |
| true |
293 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T1 |
3 |
|
T4 |
3 |
|
T93 |
1 |
| others[1] |
111 |
1 |
|
T1 |
7 |
|
T4 |
5 |
|
T138 |
7 |
| others[2] |
109 |
1 |
|
T1 |
3 |
|
T10 |
1 |
|
T4 |
3 |
| others[3] |
180 |
1 |
|
T1 |
6 |
|
T4 |
5 |
|
T138 |
11 |
| false |
53 |
1 |
|
T4 |
1 |
|
T57 |
1 |
|
T139 |
2 |
| true |
6221 |
1 |
|
T1 |
82 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T1 |
8 |
|
T16 |
1 |
|
T11 |
1 |
| others[1] |
224 |
1 |
|
T1 |
10 |
|
T4 |
3 |
|
T11 |
1 |
| others[2] |
219 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T42 |
1 |
| others[3] |
400 |
1 |
|
T1 |
17 |
|
T4 |
2 |
|
T14 |
1 |
| false |
107 |
1 |
|
T1 |
4 |
|
T138 |
3 |
|
T139 |
1 |
| true |
5613 |
1 |
|
T1 |
53 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1074 |
1 |
|
T1 |
13 |
|
T3 |
1 |
|
T10 |
1 |
| others[1] |
1063 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
1020 |
1 |
|
T1 |
25 |
|
T16 |
1 |
|
T4 |
3 |
| others[3] |
1752 |
1 |
|
T1 |
34 |
|
T4 |
3 |
|
T33 |
1 |
| false |
524 |
1 |
|
T1 |
11 |
|
T4 |
5 |
|
T138 |
5 |
| true |
1343 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T1 |
14 |
|
T14 |
1 |
|
T15 |
1 |
| others[1] |
222 |
1 |
|
T1 |
5 |
|
T4 |
2 |
|
T17 |
1 |
| others[2] |
216 |
1 |
|
T1 |
13 |
|
T6 |
1 |
|
T16 |
1 |
| others[3] |
376 |
1 |
|
T1 |
20 |
|
T4 |
3 |
|
T138 |
18 |
| false |
115 |
1 |
|
T1 |
7 |
|
T138 |
8 |
|
T57 |
3 |
| true |
5621 |
1 |
|
T1 |
42 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T1 |
8 |
|
T11 |
1 |
|
T138 |
12 |
| others[1] |
218 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T42 |
1 |
| others[2] |
224 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T138 |
15 |
| others[3] |
363 |
1 |
|
T1 |
20 |
|
T4 |
3 |
|
T17 |
1 |
| false |
105 |
1 |
|
T1 |
3 |
|
T138 |
5 |
|
T214 |
1 |
| true |
5662 |
1 |
|
T1 |
46 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1242 |
1 |
|
T1 |
19 |
|
T3 |
1 |
|
T4 |
4 |
| others[1] |
1268 |
1 |
|
T1 |
17 |
|
T10 |
1 |
|
T4 |
6 |
| others[2] |
1265 |
1 |
|
T1 |
18 |
|
T4 |
2 |
|
T5 |
1 |
| others[3] |
2071 |
1 |
|
T1 |
36 |
|
T4 |
5 |
|
T54 |
1 |
| false |
614 |
1 |
|
T1 |
11 |
|
T12 |
1 |
|
T138 |
10 |
| true |
316 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1287 |
1 |
|
T1 |
15 |
|
T4 |
4 |
|
T54 |
1 |
| others[1] |
1250 |
1 |
|
T1 |
17 |
|
T4 |
5 |
|
T5 |
1 |
| others[2] |
1272 |
1 |
|
T1 |
20 |
|
T10 |
1 |
|
T138 |
25 |
| others[3] |
2040 |
1 |
|
T1 |
37 |
|
T16 |
1 |
|
T4 |
6 |
| false |
632 |
1 |
|
T1 |
12 |
|
T4 |
2 |
|
T12 |
1 |
| true |
295 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T1 |
2 |
|
T4 |
2 |
|
T138 |
3 |
| others[1] |
117 |
1 |
|
T1 |
6 |
|
T4 |
5 |
|
T138 |
7 |
| others[2] |
97 |
1 |
|
T1 |
2 |
|
T4 |
2 |
|
T138 |
6 |
| others[3] |
187 |
1 |
|
T1 |
6 |
|
T10 |
1 |
|
T4 |
7 |
| false |
61 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T93 |
1 |
| true |
6219 |
1 |
|
T1 |
83 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
257 |
1 |
|
T1 |
10 |
|
T10 |
1 |
|
T4 |
1 |
| others[1] |
231 |
1 |
|
T1 |
11 |
|
T4 |
3 |
|
T15 |
1 |
| others[2] |
209 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T138 |
6 |
| others[3] |
364 |
1 |
|
T1 |
12 |
|
T11 |
1 |
|
T138 |
19 |
| false |
98 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T138 |
4 |
| true |
5617 |
1 |
|
T1 |
57 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
984 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T33 |
1 |
| others[1] |
1003 |
1 |
|
T1 |
19 |
|
T4 |
5 |
|
T42 |
1 |
| others[2] |
1049 |
1 |
|
T1 |
21 |
|
T4 |
3 |
|
T5 |
1 |
| others[3] |
1842 |
1 |
|
T1 |
34 |
|
T10 |
1 |
|
T4 |
5 |
| false |
513 |
1 |
|
T1 |
10 |
|
T3 |
1 |
|
T4 |
3 |
| true |
1385 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T1 |
10 |
|
T10 |
1 |
|
T4 |
1 |
| others[1] |
253 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T17 |
1 |
| others[2] |
220 |
1 |
|
T1 |
11 |
|
T84 |
1 |
|
T138 |
14 |
| others[3] |
369 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T138 |
19 |
| false |
123 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T138 |
4 |
| true |
5590 |
1 |
|
T1 |
45 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T11 |
2 |
| others[1] |
202 |
1 |
|
T1 |
9 |
|
T6 |
1 |
|
T4 |
1 |
| others[2] |
223 |
1 |
|
T1 |
16 |
|
T16 |
1 |
|
T4 |
2 |
| others[3] |
374 |
1 |
|
T1 |
22 |
|
T4 |
5 |
|
T11 |
2 |
| false |
125 |
1 |
|
T1 |
4 |
|
T17 |
1 |
|
T138 |
4 |
| true |
5627 |
1 |
|
T1 |
40 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T1 |
21 |
|
T10 |
1 |
|
T16 |
1 |
| others[1] |
1223 |
1 |
|
T1 |
20 |
|
T4 |
4 |
|
T12 |
1 |
| others[2] |
1288 |
1 |
|
T1 |
19 |
|
T4 |
1 |
|
T54 |
1 |
| others[3] |
2038 |
1 |
|
T1 |
28 |
|
T4 |
4 |
|
T84 |
1 |
| false |
648 |
1 |
|
T1 |
13 |
|
T4 |
6 |
|
T11 |
1 |
| true |
313 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T1 |
20 |
|
T4 |
5 |
|
T93 |
1 |
| others[1] |
1200 |
1 |
|
T1 |
13 |
|
T4 |
2 |
|
T54 |
1 |
| others[2] |
1244 |
1 |
|
T1 |
19 |
|
T4 |
3 |
|
T54 |
1 |
| others[3] |
2140 |
1 |
|
T1 |
35 |
|
T10 |
1 |
|
T4 |
5 |
| false |
673 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T17 |
1 |
| true |
301 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |