Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T1 |
3 |
|
T4 |
3 |
|
T138 |
6 |
| others[1] |
104 |
1 |
|
T1 |
7 |
|
T10 |
1 |
|
T4 |
2 |
| others[2] |
105 |
1 |
|
T1 |
5 |
|
T4 |
4 |
|
T93 |
1 |
| others[3] |
175 |
1 |
|
T1 |
5 |
|
T4 |
4 |
|
T12 |
1 |
| false |
42 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T138 |
3 |
| true |
6239 |
1 |
|
T1 |
81 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T1 |
9 |
|
T14 |
1 |
|
T11 |
1 |
| others[1] |
240 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T11 |
1 |
| others[2] |
230 |
1 |
|
T1 |
12 |
|
T6 |
1 |
|
T4 |
1 |
| others[3] |
352 |
1 |
|
T1 |
15 |
|
T10 |
1 |
|
T4 |
3 |
| false |
132 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T11 |
1 |
| true |
5593 |
1 |
|
T1 |
51 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1071 |
1 |
|
T1 |
21 |
|
T10 |
1 |
|
T4 |
2 |
| others[1] |
1002 |
1 |
|
T1 |
19 |
|
T4 |
2 |
|
T13 |
1 |
| others[2] |
1070 |
1 |
|
T1 |
21 |
|
T4 |
6 |
|
T83 |
1 |
| others[3] |
1787 |
1 |
|
T1 |
33 |
|
T6 |
1 |
|
T4 |
4 |
| false |
540 |
1 |
|
T1 |
7 |
|
T4 |
3 |
|
T14 |
1 |
| true |
1306 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T1 |
13 |
|
T138 |
8 |
|
T128 |
1 |
| others[1] |
228 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T84 |
1 |
| others[2] |
217 |
1 |
|
T1 |
7 |
|
T4 |
2 |
|
T15 |
1 |
| others[3] |
369 |
1 |
|
T1 |
22 |
|
T10 |
1 |
|
T16 |
1 |
| false |
130 |
1 |
|
T1 |
3 |
|
T6 |
1 |
|
T4 |
1 |
| true |
5622 |
1 |
|
T1 |
46 |
|
T3 |
1 |
|
T4 |
12 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T1 |
14 |
|
T10 |
1 |
|
T4 |
1 |
| others[1] |
201 |
1 |
|
T1 |
7 |
|
T42 |
1 |
|
T138 |
13 |
| others[2] |
229 |
1 |
|
T1 |
10 |
|
T6 |
1 |
|
T16 |
1 |
| others[3] |
371 |
1 |
|
T1 |
16 |
|
T4 |
2 |
|
T17 |
1 |
| false |
115 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T138 |
8 |
| true |
5635 |
1 |
|
T1 |
49 |
|
T3 |
1 |
|
T4 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T1 |
20 |
|
T10 |
1 |
|
T4 |
1 |
| others[1] |
1304 |
1 |
|
T1 |
17 |
|
T83 |
1 |
|
T54 |
1 |
| others[2] |
1211 |
1 |
|
T1 |
21 |
|
T4 |
4 |
|
T5 |
1 |
| others[3] |
2053 |
1 |
|
T1 |
32 |
|
T16 |
1 |
|
T4 |
10 |
| false |
632 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T138 |
9 |
| true |
317 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1257 |
1 |
|
T1 |
19 |
|
T4 |
5 |
|
T54 |
1 |
| others[1] |
1230 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
1206 |
1 |
|
T1 |
23 |
|
T4 |
1 |
|
T11 |
1 |
| others[3] |
2145 |
1 |
|
T1 |
31 |
|
T10 |
1 |
|
T4 |
9 |
| false |
647 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T15 |
1 |
| true |
291 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T138 |
3 |
| others[1] |
84 |
1 |
|
T1 |
3 |
|
T10 |
1 |
|
T93 |
1 |
| others[2] |
106 |
1 |
|
T1 |
2 |
|
T4 |
4 |
|
T138 |
8 |
| others[3] |
199 |
1 |
|
T1 |
4 |
|
T4 |
9 |
|
T138 |
5 |
| false |
44 |
1 |
|
T1 |
2 |
|
T4 |
2 |
|
T138 |
2 |
| true |
6236 |
1 |
|
T1 |
82 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T1 |
8 |
|
T4 |
5 |
|
T14 |
1 |
| others[1] |
229 |
1 |
|
T1 |
7 |
|
T10 |
1 |
|
T4 |
1 |
| others[2] |
226 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T12 |
1 |
| others[3] |
368 |
1 |
|
T1 |
21 |
|
T4 |
4 |
|
T138 |
15 |
| false |
105 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T17 |
1 |
| true |
5599 |
1 |
|
T1 |
50 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1041 |
1 |
|
T1 |
17 |
|
T4 |
4 |
|
T5 |
1 |
| others[1] |
1038 |
1 |
|
T1 |
26 |
|
T4 |
3 |
|
T82 |
1 |
| others[2] |
1058 |
1 |
|
T1 |
26 |
|
T4 |
3 |
|
T17 |
1 |
| others[3] |
1760 |
1 |
|
T1 |
25 |
|
T4 |
7 |
|
T11 |
2 |
| false |
549 |
1 |
|
T1 |
7 |
|
T10 |
1 |
|
T11 |
1 |
| true |
1330 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T1 |
8 |
|
T4 |
3 |
|
T138 |
13 |
| others[1] |
240 |
1 |
|
T1 |
7 |
|
T4 |
2 |
|
T138 |
11 |
| others[2] |
241 |
1 |
|
T1 |
6 |
|
T6 |
1 |
|
T4 |
3 |
| others[3] |
393 |
1 |
|
T1 |
20 |
|
T4 |
2 |
|
T14 |
1 |
| false |
114 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T84 |
1 |
| true |
5562 |
1 |
|
T1 |
55 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T11 |
1 |
| others[1] |
249 |
1 |
|
T1 |
13 |
|
T16 |
1 |
|
T4 |
3 |
| others[2] |
200 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T11 |
1 |
| others[3] |
390 |
1 |
|
T1 |
18 |
|
T6 |
1 |
|
T4 |
2 |
| false |
118 |
1 |
|
T1 |
4 |
|
T4 |
4 |
|
T11 |
1 |
| true |
5599 |
1 |
|
T1 |
51 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1221 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T5 |
1 |
| others[1] |
1247 |
1 |
|
T1 |
21 |
|
T10 |
1 |
|
T16 |
1 |
| others[2] |
1288 |
1 |
|
T1 |
18 |
|
T4 |
5 |
|
T138 |
16 |
| others[3] |
2077 |
1 |
|
T1 |
40 |
|
T4 |
6 |
|
T13 |
1 |
| false |
623 |
1 |
|
T1 |
8 |
|
T54 |
1 |
|
T138 |
12 |
| true |
320 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T1 |
19 |
|
T4 |
4 |
|
T54 |
1 |
| others[1] |
1287 |
1 |
|
T1 |
24 |
|
T4 |
5 |
|
T82 |
1 |
| others[2] |
1230 |
1 |
|
T1 |
22 |
|
T4 |
2 |
|
T84 |
1 |
| others[3] |
2103 |
1 |
|
T1 |
27 |
|
T4 |
6 |
|
T5 |
1 |
| false |
608 |
1 |
|
T1 |
9 |
|
T10 |
1 |
|
T138 |
10 |
| true |
297 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
86 |
1 |
|
T1 |
3 |
|
T4 |
5 |
|
T42 |
1 |
| others[1] |
108 |
1 |
|
T1 |
6 |
|
T4 |
3 |
|
T138 |
4 |
| others[2] |
114 |
1 |
|
T1 |
4 |
|
T10 |
1 |
|
T4 |
2 |
| others[3] |
192 |
1 |
|
T1 |
3 |
|
T4 |
5 |
|
T12 |
1 |
| false |
53 |
1 |
|
T1 |
2 |
|
T4 |
2 |
|
T131 |
1 |
| true |
6223 |
1 |
|
T1 |
83 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T93 |
1 |
| others[1] |
212 |
1 |
|
T1 |
6 |
|
T4 |
4 |
|
T14 |
1 |
| others[2] |
249 |
1 |
|
T1 |
8 |
|
T4 |
3 |
|
T138 |
10 |
| others[3] |
417 |
1 |
|
T1 |
14 |
|
T10 |
1 |
|
T4 |
1 |
| false |
112 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T11 |
2 |
| true |
5550 |
1 |
|
T1 |
65 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1086 |
1 |
|
T1 |
12 |
|
T6 |
1 |
|
T10 |
1 |
| others[1] |
1040 |
1 |
|
T1 |
21 |
|
T3 |
1 |
|
T4 |
3 |
| others[2] |
1068 |
1 |
|
T1 |
24 |
|
T16 |
1 |
|
T4 |
2 |
| others[3] |
1765 |
1 |
|
T1 |
35 |
|
T4 |
9 |
|
T82 |
1 |
| false |
520 |
1 |
|
T1 |
9 |
|
T11 |
1 |
|
T93 |
1 |
| true |
1297 |
1 |
|
T17 |
1 |
|
T14 |
1 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T138 |
7 |
| others[1] |
215 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T138 |
15 |
| others[2] |
257 |
1 |
|
T1 |
13 |
|
T6 |
1 |
|
T4 |
2 |
| others[3] |
387 |
1 |
|
T1 |
19 |
|
T4 |
2 |
|
T42 |
1 |
| false |
118 |
1 |
|
T1 |
4 |
|
T138 |
8 |
|
T227 |
1 |
| true |
5596 |
1 |
|
T1 |
51 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T1 |
14 |
|
T10 |
1 |
|
T138 |
9 |
| others[1] |
231 |
1 |
|
T1 |
9 |
|
T11 |
1 |
|
T138 |
12 |
| others[2] |
211 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T138 |
10 |
| others[3] |
359 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T13 |
1 |
| false |
124 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T138 |
3 |
| true |
5628 |
1 |
|
T1 |
47 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T1 |
18 |
|
T16 |
1 |
|
T4 |
3 |
| others[1] |
1231 |
1 |
|
T1 |
21 |
|
T4 |
4 |
|
T12 |
1 |
| others[2] |
1279 |
1 |
|
T1 |
17 |
|
T10 |
1 |
|
T4 |
6 |
| others[3] |
2073 |
1 |
|
T1 |
35 |
|
T4 |
3 |
|
T54 |
1 |
| false |
623 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T13 |
1 |
| true |
332 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1209 |
1 |
|
T1 |
18 |
|
T10 |
1 |
|
T4 |
5 |
| others[1] |
1286 |
1 |
|
T1 |
26 |
|
T4 |
3 |
|
T138 |
19 |
| others[2] |
1232 |
1 |
|
T1 |
16 |
|
T4 |
4 |
|
T5 |
1 |
| others[3] |
2095 |
1 |
|
T1 |
35 |
|
T4 |
4 |
|
T12 |
1 |
| false |
652 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T138 |
15 |
| true |
302 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
3 |
| others[1] |
117 |
1 |
|
T1 |
7 |
|
T16 |
1 |
|
T4 |
4 |
| others[2] |
103 |
1 |
|
T1 |
3 |
|
T4 |
2 |
|
T138 |
8 |
| others[3] |
173 |
1 |
|
T1 |
12 |
|
T4 |
6 |
|
T13 |
1 |
| false |
55 |
1 |
|
T1 |
3 |
|
T4 |
2 |
|
T12 |
1 |
| true |
6227 |
1 |
|
T1 |
75 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T42 |
1 |
| others[1] |
239 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T138 |
12 |
| others[2] |
229 |
1 |
|
T1 |
6 |
|
T10 |
1 |
|
T4 |
3 |
| others[3] |
368 |
1 |
|
T1 |
16 |
|
T6 |
1 |
|
T4 |
1 |
| false |
118 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T11 |
2 |
| true |
5614 |
1 |
|
T1 |
56 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1076 |
1 |
|
T1 |
21 |
|
T3 |
1 |
|
T4 |
3 |
| others[1] |
1016 |
1 |
|
T1 |
20 |
|
T10 |
1 |
|
T16 |
1 |
| others[2] |
1010 |
1 |
|
T1 |
17 |
|
T4 |
5 |
|
T42 |
1 |
| others[3] |
1744 |
1 |
|
T1 |
33 |
|
T6 |
1 |
|
T4 |
6 |
| false |
562 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T54 |
2 |
| true |
1368 |
1 |
|
T17 |
1 |
|
T14 |
1 |
|
T82 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T138 |
10 |
| others[1] |
247 |
1 |
|
T1 |
13 |
|
T10 |
1 |
|
T84 |
1 |
| others[2] |
199 |
1 |
|
T1 |
5 |
|
T14 |
1 |
|
T138 |
8 |
| others[3] |
360 |
1 |
|
T1 |
15 |
|
T4 |
5 |
|
T138 |
13 |
| false |
139 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T138 |
10 |
| true |
5626 |
1 |
|
T1 |
49 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T1 |
8 |
|
T16 |
1 |
|
T4 |
3 |
| others[1] |
217 |
1 |
|
T1 |
5 |
|
T4 |
5 |
|
T138 |
11 |
| others[2] |
213 |
1 |
|
T1 |
7 |
|
T138 |
7 |
|
T214 |
1 |
| others[3] |
359 |
1 |
|
T1 |
22 |
|
T10 |
1 |
|
T4 |
1 |
| false |
96 |
1 |
|
T1 |
5 |
|
T84 |
1 |
|
T138 |
3 |
| true |
5661 |
1 |
|
T1 |
54 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1255 |
1 |
|
T1 |
19 |
|
T16 |
1 |
|
T4 |
2 |
| others[1] |
1232 |
1 |
|
T1 |
27 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
1259 |
1 |
|
T1 |
21 |
|
T10 |
1 |
|
T4 |
1 |
| others[3] |
2090 |
1 |
|
T1 |
22 |
|
T4 |
8 |
|
T83 |
1 |
| false |
605 |
1 |
|
T1 |
12 |
|
T4 |
4 |
|
T138 |
6 |
| true |
335 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T1 |
15 |
|
T10 |
1 |
|
T4 |
4 |
| others[1] |
1251 |
1 |
|
T1 |
17 |
|
T4 |
4 |
|
T54 |
1 |
| others[2] |
1244 |
1 |
|
T1 |
23 |
|
T16 |
1 |
|
T4 |
5 |
| others[3] |
2062 |
1 |
|
T1 |
37 |
|
T4 |
2 |
|
T12 |
1 |
| false |
662 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T13 |
1 |
| true |
299 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T1 |
6 |
|
T4 |
5 |
|
T138 |
4 |
| others[1] |
88 |
1 |
|
T1 |
1 |
|
T138 |
4 |
|
T57 |
1 |
| others[2] |
108 |
1 |
|
T1 |
4 |
|
T4 |
5 |
|
T138 |
4 |
| others[3] |
193 |
1 |
|
T1 |
6 |
|
T4 |
5 |
|
T12 |
1 |
| false |
66 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
2 |
| true |
6224 |
1 |
|
T1 |
83 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T1 |
9 |
|
T42 |
1 |
|
T11 |
3 |
| others[1] |
226 |
1 |
|
T1 |
14 |
|
T4 |
3 |
|
T11 |
2 |
| others[2] |
217 |
1 |
|
T1 |
7 |
|
T6 |
1 |
|
T4 |
2 |
| others[3] |
390 |
1 |
|
T1 |
22 |
|
T4 |
5 |
|
T12 |
1 |
| false |
111 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T138 |
3 |
| true |
5601 |
1 |
|
T1 |
44 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1051 |
1 |
|
T1 |
21 |
|
T10 |
1 |
|
T4 |
3 |
| others[1] |
1080 |
1 |
|
T1 |
20 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
1066 |
1 |
|
T1 |
18 |
|
T4 |
4 |
|
T13 |
1 |
| others[3] |
1685 |
1 |
|
T1 |
34 |
|
T16 |
1 |
|
T4 |
5 |
| false |
540 |
1 |
|
T1 |
8 |
|
T4 |
3 |
|
T138 |
7 |
| true |
1354 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |