Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T1 |
11 |
|
T138 |
12 |
|
T55 |
1 |
| others[1] |
257 |
1 |
|
T1 |
8 |
|
T15 |
1 |
|
T13 |
1 |
| others[2] |
215 |
1 |
|
T1 |
13 |
|
T138 |
10 |
|
T228 |
1 |
| others[3] |
386 |
1 |
|
T1 |
19 |
|
T4 |
3 |
|
T17 |
1 |
| false |
122 |
1 |
|
T1 |
9 |
|
T16 |
1 |
|
T138 |
5 |
| true |
5590 |
1 |
|
T1 |
41 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T11 |
1 |
| others[1] |
230 |
1 |
|
T1 |
13 |
|
T6 |
1 |
|
T16 |
1 |
| others[2] |
243 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T12 |
1 |
| others[3] |
388 |
1 |
|
T1 |
14 |
|
T4 |
5 |
|
T11 |
2 |
| false |
118 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T138 |
4 |
| true |
5583 |
1 |
|
T1 |
50 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T1 |
20 |
|
T4 |
3 |
|
T12 |
1 |
| others[1] |
1274 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T54 |
1 |
| others[2] |
1215 |
1 |
|
T1 |
16 |
|
T4 |
4 |
|
T82 |
1 |
| others[3] |
2035 |
1 |
|
T1 |
38 |
|
T4 |
4 |
|
T5 |
1 |
| false |
682 |
1 |
|
T1 |
10 |
|
T10 |
1 |
|
T4 |
5 |
| true |
322 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1232 |
1 |
|
T1 |
19 |
|
T4 |
6 |
|
T93 |
1 |
| others[1] |
1224 |
1 |
|
T1 |
16 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
1230 |
1 |
|
T1 |
21 |
|
T10 |
1 |
|
T4 |
6 |
| others[3] |
2118 |
1 |
|
T1 |
34 |
|
T4 |
1 |
|
T12 |
1 |
| false |
677 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T138 |
12 |
| true |
295 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T4 |
3 |
|
T138 |
4 |
|
T61 |
1 |
| others[1] |
109 |
1 |
|
T1 |
2 |
|
T4 |
2 |
|
T138 |
3 |
| others[2] |
93 |
1 |
|
T1 |
4 |
|
T4 |
3 |
|
T13 |
1 |
| others[3] |
174 |
1 |
|
T1 |
9 |
|
T10 |
1 |
|
T4 |
6 |
| false |
74 |
1 |
|
T1 |
5 |
|
T4 |
3 |
|
T138 |
3 |
| true |
6227 |
1 |
|
T1 |
81 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T1 |
7 |
|
T6 |
1 |
|
T17 |
1 |
| others[1] |
216 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T42 |
1 |
| others[2] |
244 |
1 |
|
T1 |
11 |
|
T4 |
3 |
|
T138 |
10 |
| others[3] |
379 |
1 |
|
T1 |
19 |
|
T4 |
4 |
|
T138 |
16 |
| false |
119 |
1 |
|
T1 |
6 |
|
T16 |
1 |
|
T4 |
1 |
| true |
5577 |
1 |
|
T1 |
43 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1091 |
1 |
|
T1 |
15 |
|
T4 |
3 |
|
T11 |
1 |
| others[1] |
994 |
1 |
|
T1 |
19 |
|
T10 |
1 |
|
T4 |
2 |
| others[2] |
1045 |
1 |
|
T1 |
15 |
|
T3 |
1 |
|
T4 |
3 |
| others[3] |
1843 |
1 |
|
T1 |
44 |
|
T4 |
7 |
|
T11 |
1 |
| false |
512 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T14 |
1 |
| true |
1291 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T93 |
1 |
| others[1] |
228 |
1 |
|
T1 |
12 |
|
T10 |
1 |
|
T4 |
1 |
| others[2] |
203 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T138 |
11 |
| others[3] |
342 |
1 |
|
T1 |
17 |
|
T6 |
1 |
|
T4 |
1 |
| false |
109 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T138 |
6 |
| true |
5649 |
1 |
|
T1 |
46 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T138 |
10 |
| others[1] |
227 |
1 |
|
T1 |
9 |
|
T11 |
1 |
|
T12 |
1 |
| others[2] |
239 |
1 |
|
T1 |
13 |
|
T10 |
1 |
|
T4 |
2 |
| others[3] |
363 |
1 |
|
T1 |
17 |
|
T4 |
5 |
|
T84 |
1 |
| false |
100 |
1 |
|
T1 |
4 |
|
T138 |
6 |
|
T227 |
1 |
| true |
5633 |
1 |
|
T1 |
47 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1189 |
1 |
|
T1 |
25 |
|
T10 |
1 |
|
T4 |
6 |
| others[1] |
1239 |
1 |
|
T1 |
22 |
|
T4 |
5 |
|
T138 |
21 |
| others[2] |
1255 |
1 |
|
T1 |
21 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
2088 |
1 |
|
T1 |
25 |
|
T4 |
3 |
|
T12 |
1 |
| false |
667 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T138 |
9 |
| true |
338 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T1 |
22 |
|
T4 |
4 |
|
T138 |
16 |
| others[1] |
1258 |
1 |
|
T1 |
21 |
|
T4 |
2 |
|
T93 |
1 |
| others[2] |
1282 |
1 |
|
T1 |
25 |
|
T4 |
4 |
|
T54 |
1 |
| others[3] |
2060 |
1 |
|
T1 |
26 |
|
T3 |
1 |
|
T10 |
1 |
| false |
629 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T54 |
1 |
| true |
296 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T1 |
8 |
|
T4 |
4 |
|
T138 |
4 |
| others[1] |
125 |
1 |
|
T1 |
4 |
|
T10 |
1 |
|
T4 |
4 |
| others[2] |
117 |
1 |
|
T1 |
7 |
|
T4 |
6 |
|
T12 |
1 |
| others[3] |
161 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T138 |
4 |
| false |
51 |
1 |
|
T1 |
1 |
|
T4 |
2 |
|
T138 |
1 |
| true |
6226 |
1 |
|
T1 |
80 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T1 |
11 |
|
T11 |
2 |
|
T138 |
7 |
| others[1] |
232 |
1 |
|
T1 |
11 |
|
T4 |
3 |
|
T11 |
1 |
| others[2] |
204 |
1 |
|
T1 |
5 |
|
T10 |
1 |
|
T4 |
2 |
| others[3] |
388 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T11 |
1 |
| false |
97 |
1 |
|
T1 |
4 |
|
T138 |
2 |
|
T40 |
1 |
| true |
5622 |
1 |
|
T1 |
54 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1023 |
1 |
|
T1 |
14 |
|
T4 |
5 |
|
T11 |
1 |
| others[1] |
1036 |
1 |
|
T1 |
22 |
|
T3 |
1 |
|
T4 |
2 |
| others[2] |
1043 |
1 |
|
T1 |
22 |
|
T10 |
1 |
|
T4 |
2 |
| others[3] |
1817 |
1 |
|
T1 |
29 |
|
T16 |
1 |
|
T4 |
8 |
| false |
523 |
1 |
|
T1 |
14 |
|
T42 |
1 |
|
T54 |
1 |
| true |
1334 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T1 |
10 |
|
T15 |
1 |
|
T138 |
7 |
| others[1] |
204 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T84 |
1 |
| others[2] |
241 |
1 |
|
T1 |
11 |
|
T4 |
4 |
|
T93 |
1 |
| others[3] |
374 |
1 |
|
T1 |
15 |
|
T16 |
1 |
|
T4 |
3 |
| false |
103 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T138 |
6 |
| true |
5623 |
1 |
|
T1 |
49 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T1 |
10 |
|
T10 |
1 |
|
T4 |
1 |
| others[1] |
208 |
1 |
|
T1 |
5 |
|
T4 |
3 |
|
T11 |
1 |
| others[2] |
242 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T138 |
5 |
| others[3] |
345 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T138 |
12 |
| false |
132 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T93 |
1 |
| true |
5641 |
1 |
|
T1 |
54 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1284 |
1 |
|
T1 |
23 |
|
T4 |
2 |
|
T54 |
1 |
| others[1] |
1224 |
1 |
|
T1 |
16 |
|
T4 |
4 |
|
T15 |
1 |
| others[2] |
1223 |
1 |
|
T1 |
20 |
|
T4 |
2 |
|
T138 |
25 |
| others[3] |
2062 |
1 |
|
T1 |
30 |
|
T10 |
1 |
|
T16 |
1 |
| false |
648 |
1 |
|
T1 |
12 |
|
T4 |
3 |
|
T138 |
11 |
| true |
335 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1281 |
1 |
|
T1 |
17 |
|
T10 |
1 |
|
T16 |
1 |
| others[1] |
1259 |
1 |
|
T1 |
19 |
|
T4 |
3 |
|
T13 |
1 |
| others[2] |
1264 |
1 |
|
T1 |
21 |
|
T4 |
3 |
|
T93 |
1 |
| others[3] |
2022 |
1 |
|
T1 |
27 |
|
T4 |
4 |
|
T82 |
1 |
| false |
655 |
1 |
|
T1 |
17 |
|
T4 |
2 |
|
T5 |
1 |
| true |
295 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T1 |
3 |
|
T4 |
3 |
|
T93 |
1 |
| others[1] |
119 |
1 |
|
T1 |
5 |
|
T4 |
3 |
|
T84 |
1 |
| others[2] |
100 |
1 |
|
T1 |
3 |
|
T4 |
5 |
|
T13 |
1 |
| others[3] |
189 |
1 |
|
T1 |
5 |
|
T4 |
3 |
|
T138 |
6 |
| false |
54 |
1 |
|
T10 |
1 |
|
T4 |
3 |
|
T57 |
2 |
| true |
6209 |
1 |
|
T1 |
85 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T1 |
8 |
|
T42 |
1 |
|
T138 |
12 |
| others[1] |
227 |
1 |
|
T1 |
9 |
|
T4 |
3 |
|
T138 |
14 |
| others[2] |
205 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T14 |
1 |
| others[3] |
359 |
1 |
|
T1 |
12 |
|
T6 |
1 |
|
T4 |
3 |
| false |
118 |
1 |
|
T1 |
2 |
|
T4 |
2 |
|
T13 |
1 |
| true |
5636 |
1 |
|
T1 |
60 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1046 |
1 |
|
T1 |
11 |
|
T10 |
1 |
|
T4 |
3 |
| others[1] |
1066 |
1 |
|
T1 |
23 |
|
T4 |
4 |
|
T17 |
1 |
| others[2] |
1047 |
1 |
|
T1 |
21 |
|
T6 |
1 |
|
T16 |
1 |
| others[3] |
1722 |
1 |
|
T1 |
37 |
|
T4 |
7 |
|
T5 |
1 |
| false |
572 |
1 |
|
T1 |
9 |
|
T3 |
1 |
|
T4 |
1 |
| true |
1323 |
1 |
|
T82 |
1 |
|
T15 |
1 |
|
T11 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T1 |
16 |
|
T10 |
1 |
|
T138 |
8 |
| others[1] |
216 |
1 |
|
T1 |
5 |
|
T4 |
2 |
|
T138 |
7 |
| others[2] |
217 |
1 |
|
T1 |
8 |
|
T4 |
4 |
|
T42 |
1 |
| others[3] |
412 |
1 |
|
T1 |
20 |
|
T4 |
3 |
|
T12 |
1 |
| false |
115 |
1 |
|
T1 |
6 |
|
T138 |
4 |
|
T228 |
1 |
| true |
5577 |
1 |
|
T1 |
46 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T138 |
9 |
| others[1] |
236 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T138 |
13 |
| others[2] |
217 |
1 |
|
T1 |
11 |
|
T10 |
1 |
|
T4 |
2 |
| others[3] |
332 |
1 |
|
T1 |
11 |
|
T4 |
5 |
|
T11 |
2 |
| false |
105 |
1 |
|
T1 |
6 |
|
T4 |
4 |
|
T11 |
1 |
| true |
5647 |
1 |
|
T1 |
47 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1192 |
1 |
|
T1 |
16 |
|
T3 |
1 |
|
T4 |
2 |
| others[1] |
1249 |
1 |
|
T1 |
20 |
|
T10 |
1 |
|
T4 |
2 |
| others[2] |
1265 |
1 |
|
T1 |
17 |
|
T4 |
2 |
|
T12 |
1 |
| others[3] |
2076 |
1 |
|
T1 |
36 |
|
T4 |
7 |
|
T138 |
35 |
| false |
658 |
1 |
|
T1 |
12 |
|
T4 |
4 |
|
T54 |
1 |
| true |
336 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1225 |
1 |
|
T1 |
13 |
|
T4 |
3 |
|
T138 |
25 |
| others[1] |
1242 |
1 |
|
T1 |
27 |
|
T4 |
6 |
|
T11 |
1 |
| others[2] |
1251 |
1 |
|
T1 |
23 |
|
T4 |
3 |
|
T5 |
1 |
| others[3] |
2107 |
1 |
|
T1 |
26 |
|
T3 |
1 |
|
T10 |
1 |
| false |
653 |
1 |
|
T1 |
12 |
|
T138 |
5 |
|
T30 |
2 |
| true |
298 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
121 |
1 |
|
T1 |
8 |
|
T4 |
3 |
|
T138 |
3 |
| others[1] |
93 |
1 |
|
T4 |
2 |
|
T84 |
1 |
|
T138 |
3 |
| others[2] |
97 |
1 |
|
T4 |
3 |
|
T138 |
4 |
|
T128 |
1 |
| others[3] |
175 |
1 |
|
T1 |
4 |
|
T10 |
1 |
|
T4 |
8 |
| false |
51 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T93 |
1 |
| true |
6239 |
1 |
|
T1 |
88 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
197 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T138 |
10 |
| others[1] |
225 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T11 |
1 |
| others[2] |
242 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T11 |
1 |
| others[3] |
397 |
1 |
|
T1 |
20 |
|
T4 |
3 |
|
T42 |
1 |
| false |
118 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T15 |
1 |
| true |
5597 |
1 |
|
T1 |
51 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1059 |
1 |
|
T1 |
21 |
|
T10 |
1 |
|
T4 |
4 |
| others[1] |
1050 |
1 |
|
T1 |
24 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
1036 |
1 |
|
T1 |
19 |
|
T4 |
5 |
|
T11 |
1 |
| others[3] |
1797 |
1 |
|
T1 |
28 |
|
T4 |
7 |
|
T15 |
1 |
| false |
553 |
1 |
|
T1 |
9 |
|
T138 |
9 |
|
T30 |
2 |
| true |
1281 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T138 |
13 |
| others[1] |
203 |
1 |
|
T1 |
10 |
|
T4 |
3 |
|
T138 |
6 |
| others[2] |
217 |
1 |
|
T1 |
11 |
|
T6 |
1 |
|
T4 |
1 |
| others[3] |
369 |
1 |
|
T1 |
14 |
|
T16 |
1 |
|
T4 |
1 |
| false |
108 |
1 |
|
T1 |
3 |
|
T17 |
1 |
|
T57 |
3 |
| true |
5652 |
1 |
|
T1 |
53 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T1 |
7 |
|
T4 |
3 |
|
T11 |
1 |
| others[1] |
214 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T13 |
1 |
| others[2] |
249 |
1 |
|
T1 |
14 |
|
T4 |
3 |
|
T11 |
1 |
| others[3] |
358 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T11 |
1 |
| false |
98 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T138 |
6 |
| true |
5647 |
1 |
|
T1 |
49 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1286 |
1 |
|
T1 |
22 |
|
T4 |
4 |
|
T17 |
1 |
| others[1] |
1297 |
1 |
|
T1 |
16 |
|
T16 |
1 |
|
T4 |
3 |
| others[2] |
1185 |
1 |
|
T1 |
19 |
|
T4 |
3 |
|
T5 |
1 |
| others[3] |
2041 |
1 |
|
T1 |
33 |
|
T10 |
1 |
|
T4 |
7 |
| false |
636 |
1 |
|
T1 |
11 |
|
T12 |
1 |
|
T138 |
13 |
| true |
331 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T14 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |