Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1300 |
1 |
|
T1 |
25 |
|
T4 |
5 |
|
T15 |
1 |
| others[1] |
1298 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T138 |
21 |
| others[2] |
1202 |
1 |
|
T1 |
23 |
|
T4 |
2 |
|
T138 |
23 |
| others[3] |
2066 |
1 |
|
T1 |
29 |
|
T10 |
1 |
|
T4 |
8 |
| false |
612 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T13 |
1 |
| true |
298 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T93 |
1 |
| others[1] |
114 |
1 |
|
T1 |
8 |
|
T4 |
8 |
|
T138 |
1 |
| others[2] |
97 |
1 |
|
T1 |
3 |
|
T4 |
3 |
|
T12 |
1 |
| others[3] |
166 |
1 |
|
T1 |
5 |
|
T10 |
1 |
|
T4 |
2 |
| false |
50 |
1 |
|
T1 |
6 |
|
T4 |
3 |
|
T138 |
5 |
| true |
6242 |
1 |
|
T1 |
74 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T138 |
6 |
| others[1] |
223 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T42 |
1 |
| others[2] |
224 |
1 |
|
T1 |
12 |
|
T4 |
2 |
|
T11 |
1 |
| others[3] |
374 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T11 |
2 |
| false |
120 |
1 |
|
T1 |
5 |
|
T10 |
1 |
|
T4 |
1 |
| true |
5627 |
1 |
|
T1 |
56 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1090 |
1 |
|
T1 |
21 |
|
T4 |
4 |
|
T11 |
2 |
| others[1] |
1029 |
1 |
|
T1 |
18 |
|
T4 |
3 |
|
T14 |
1 |
| others[2] |
1075 |
1 |
|
T1 |
16 |
|
T3 |
1 |
|
T16 |
1 |
| others[3] |
1740 |
1 |
|
T1 |
35 |
|
T10 |
1 |
|
T4 |
4 |
| false |
532 |
1 |
|
T1 |
11 |
|
T4 |
3 |
|
T138 |
13 |
| true |
1310 |
1 |
|
T6 |
1 |
|
T82 |
1 |
|
T83 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
288 |
1 |
|
T1 |
10 |
|
T6 |
1 |
|
T16 |
1 |
| others[1] |
201 |
1 |
|
T1 |
9 |
|
T4 |
3 |
|
T138 |
4 |
| others[2] |
216 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T14 |
1 |
| others[3] |
358 |
1 |
|
T1 |
18 |
|
T10 |
1 |
|
T4 |
3 |
| false |
111 |
1 |
|
T1 |
6 |
|
T17 |
1 |
|
T138 |
7 |
| true |
5602 |
1 |
|
T1 |
47 |
|
T3 |
1 |
|
T4 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T1 |
9 |
|
T4 |
3 |
|
T13 |
1 |
| others[1] |
202 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T12 |
1 |
| others[2] |
230 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T11 |
1 |
| others[3] |
358 |
1 |
|
T1 |
15 |
|
T6 |
1 |
|
T4 |
5 |
| false |
121 |
1 |
|
T1 |
5 |
|
T138 |
5 |
|
T128 |
1 |
| true |
5661 |
1 |
|
T1 |
52 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T1 |
19 |
|
T4 |
4 |
|
T13 |
1 |
| others[1] |
1220 |
1 |
|
T1 |
28 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
1255 |
1 |
|
T1 |
17 |
|
T10 |
1 |
|
T4 |
2 |
| others[3] |
2094 |
1 |
|
T1 |
25 |
|
T4 |
8 |
|
T54 |
2 |
| false |
643 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T12 |
1 |
| true |
326 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1291 |
1 |
|
T1 |
23 |
|
T4 |
3 |
|
T5 |
1 |
| others[1] |
1246 |
1 |
|
T1 |
22 |
|
T4 |
2 |
|
T93 |
1 |
| others[2] |
1247 |
1 |
|
T1 |
24 |
|
T10 |
1 |
|
T4 |
3 |
| others[3] |
2055 |
1 |
|
T1 |
24 |
|
T4 |
7 |
|
T12 |
1 |
| false |
640 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T138 |
8 |
| true |
297 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T138 |
5 |
| others[1] |
105 |
1 |
|
T1 |
3 |
|
T4 |
5 |
|
T138 |
3 |
| others[2] |
101 |
1 |
|
T1 |
7 |
|
T4 |
2 |
|
T138 |
1 |
| others[3] |
174 |
1 |
|
T1 |
10 |
|
T10 |
1 |
|
T4 |
5 |
| false |
67 |
1 |
|
T1 |
2 |
|
T4 |
4 |
|
T138 |
1 |
| true |
6234 |
1 |
|
T1 |
75 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T1 |
11 |
|
T10 |
1 |
|
T11 |
1 |
| others[1] |
229 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T93 |
1 |
| others[2] |
216 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T11 |
1 |
| others[3] |
377 |
1 |
|
T1 |
14 |
|
T6 |
1 |
|
T4 |
4 |
| false |
136 |
1 |
|
T1 |
6 |
|
T16 |
1 |
|
T4 |
1 |
| true |
5591 |
1 |
|
T1 |
53 |
|
T3 |
1 |
|
T4 |
10 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1078 |
1 |
|
T1 |
26 |
|
T4 |
1 |
|
T83 |
1 |
| others[1] |
1037 |
1 |
|
T1 |
14 |
|
T16 |
1 |
|
T4 |
3 |
| others[2] |
1050 |
1 |
|
T1 |
15 |
|
T10 |
1 |
|
T4 |
5 |
| others[3] |
1745 |
1 |
|
T1 |
34 |
|
T4 |
5 |
|
T5 |
1 |
| false |
563 |
1 |
|
T1 |
12 |
|
T4 |
3 |
|
T14 |
1 |
| true |
1303 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T1 |
14 |
|
T10 |
1 |
|
T16 |
1 |
| others[1] |
209 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T12 |
1 |
| others[2] |
229 |
1 |
|
T1 |
7 |
|
T6 |
1 |
|
T4 |
3 |
| others[3] |
413 |
1 |
|
T1 |
16 |
|
T14 |
1 |
|
T93 |
1 |
| false |
119 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T42 |
1 |
| true |
5600 |
1 |
|
T1 |
47 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T11 |
1 |
| others[1] |
198 |
1 |
|
T1 |
9 |
|
T42 |
1 |
|
T11 |
1 |
| others[2] |
198 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T11 |
1 |
| others[3] |
355 |
1 |
|
T1 |
18 |
|
T4 |
2 |
|
T17 |
1 |
| false |
121 |
1 |
|
T1 |
6 |
|
T138 |
7 |
|
T130 |
1 |
| true |
5663 |
1 |
|
T1 |
50 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1286 |
1 |
|
T1 |
28 |
|
T4 |
5 |
|
T138 |
21 |
| others[1] |
1230 |
1 |
|
T1 |
10 |
|
T10 |
1 |
|
T4 |
4 |
| others[2] |
1257 |
1 |
|
T1 |
12 |
|
T4 |
4 |
|
T5 |
1 |
| others[3] |
2078 |
1 |
|
T1 |
41 |
|
T4 |
3 |
|
T54 |
2 |
| false |
596 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T138 |
9 |
| true |
329 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1209 |
1 |
|
T1 |
18 |
|
T4 |
2 |
|
T138 |
9 |
| others[1] |
1283 |
1 |
|
T1 |
17 |
|
T10 |
1 |
|
T4 |
3 |
| others[2] |
1251 |
1 |
|
T1 |
25 |
|
T4 |
5 |
|
T5 |
1 |
| others[3] |
2119 |
1 |
|
T1 |
31 |
|
T16 |
1 |
|
T4 |
5 |
| false |
619 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T11 |
1 |
| true |
295 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
120 |
1 |
|
T1 |
2 |
|
T4 |
2 |
|
T93 |
1 |
| others[1] |
91 |
1 |
|
T1 |
4 |
|
T4 |
3 |
|
T84 |
1 |
| others[2] |
104 |
1 |
|
T1 |
4 |
|
T4 |
7 |
|
T138 |
2 |
| others[3] |
187 |
1 |
|
T1 |
6 |
|
T10 |
1 |
|
T4 |
4 |
| false |
67 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T42 |
1 |
| true |
6207 |
1 |
|
T1 |
83 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T1 |
9 |
|
T6 |
1 |
|
T10 |
1 |
| others[1] |
238 |
1 |
|
T1 |
14 |
|
T14 |
1 |
|
T42 |
1 |
| others[2] |
225 |
1 |
|
T1 |
10 |
|
T138 |
6 |
|
T57 |
4 |
| others[3] |
382 |
1 |
|
T1 |
15 |
|
T16 |
1 |
|
T4 |
2 |
| false |
132 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T138 |
3 |
| true |
5558 |
1 |
|
T1 |
47 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1027 |
1 |
|
T1 |
19 |
|
T4 |
4 |
|
T82 |
1 |
| others[1] |
1028 |
1 |
|
T1 |
19 |
|
T4 |
3 |
|
T5 |
1 |
| others[2] |
1035 |
1 |
|
T1 |
16 |
|
T3 |
1 |
|
T4 |
3 |
| others[3] |
1779 |
1 |
|
T1 |
35 |
|
T10 |
1 |
|
T4 |
4 |
| false |
546 |
1 |
|
T1 |
12 |
|
T4 |
3 |
|
T138 |
10 |
| true |
1361 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T83 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
200 |
1 |
|
T1 |
13 |
|
T4 |
1 |
|
T138 |
9 |
| others[1] |
226 |
1 |
|
T1 |
13 |
|
T15 |
1 |
|
T93 |
1 |
| others[2] |
220 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T138 |
14 |
| others[3] |
380 |
1 |
|
T1 |
10 |
|
T6 |
1 |
|
T4 |
2 |
| false |
126 |
1 |
|
T1 |
6 |
|
T4 |
2 |
|
T138 |
4 |
| true |
5624 |
1 |
|
T1 |
50 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T1 |
12 |
|
T16 |
1 |
|
T4 |
2 |
| others[1] |
227 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T17 |
1 |
| others[2] |
214 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T138 |
11 |
| others[3] |
366 |
1 |
|
T1 |
22 |
|
T4 |
2 |
|
T42 |
1 |
| false |
115 |
1 |
|
T1 |
4 |
|
T4 |
2 |
|
T11 |
1 |
| true |
5621 |
1 |
|
T1 |
41 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T1 |
25 |
|
T4 |
5 |
|
T12 |
1 |
| others[1] |
1242 |
1 |
|
T1 |
18 |
|
T10 |
1 |
|
T4 |
5 |
| others[2] |
1225 |
1 |
|
T1 |
14 |
|
T42 |
1 |
|
T93 |
1 |
| others[3] |
2077 |
1 |
|
T1 |
29 |
|
T4 |
2 |
|
T13 |
1 |
| false |
640 |
1 |
|
T1 |
15 |
|
T4 |
5 |
|
T5 |
1 |
| true |
327 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1214 |
1 |
|
T1 |
16 |
|
T4 |
4 |
|
T54 |
1 |
| others[1] |
1254 |
1 |
|
T1 |
21 |
|
T10 |
1 |
|
T4 |
3 |
| others[2] |
1181 |
1 |
|
T1 |
23 |
|
T4 |
2 |
|
T13 |
1 |
| others[3] |
2129 |
1 |
|
T1 |
29 |
|
T4 |
7 |
|
T5 |
1 |
| false |
695 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T12 |
1 |
| true |
303 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T1 |
3 |
|
T10 |
1 |
|
T4 |
3 |
| others[1] |
91 |
1 |
|
T1 |
3 |
|
T4 |
4 |
|
T138 |
6 |
| others[2] |
116 |
1 |
|
T1 |
3 |
|
T4 |
3 |
|
T12 |
1 |
| others[3] |
164 |
1 |
|
T1 |
8 |
|
T4 |
5 |
|
T138 |
11 |
| false |
57 |
1 |
|
T1 |
3 |
|
T4 |
2 |
|
T84 |
1 |
| true |
6246 |
1 |
|
T1 |
81 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T1 |
9 |
|
T11 |
1 |
|
T138 |
7 |
| others[1] |
248 |
1 |
|
T1 |
9 |
|
T6 |
1 |
|
T10 |
1 |
| others[2] |
208 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T11 |
1 |
| others[3] |
373 |
1 |
|
T1 |
16 |
|
T4 |
2 |
|
T15 |
1 |
| false |
114 |
1 |
|
T1 |
7 |
|
T16 |
1 |
|
T4 |
1 |
| true |
5603 |
1 |
|
T1 |
50 |
|
T3 |
1 |
|
T4 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1038 |
1 |
|
T1 |
23 |
|
T10 |
1 |
|
T83 |
1 |
| others[1] |
1071 |
1 |
|
T1 |
21 |
|
T4 |
5 |
|
T15 |
1 |
| others[2] |
1025 |
1 |
|
T1 |
20 |
|
T4 |
3 |
|
T5 |
1 |
| others[3] |
1722 |
1 |
|
T1 |
29 |
|
T4 |
7 |
|
T42 |
1 |
| false |
560 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T17 |
1 |
| true |
1360 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T93 |
1 |
| others[1] |
229 |
1 |
|
T1 |
11 |
|
T6 |
1 |
|
T4 |
1 |
| others[2] |
189 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T13 |
1 |
| others[3] |
391 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T15 |
1 |
| false |
121 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T42 |
1 |
| true |
5620 |
1 |
|
T1 |
65 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T1 |
9 |
|
T10 |
1 |
|
T4 |
2 |
| others[1] |
220 |
1 |
|
T1 |
6 |
|
T4 |
2 |
|
T11 |
1 |
| others[2] |
200 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T138 |
9 |
| others[3] |
375 |
1 |
|
T1 |
21 |
|
T16 |
1 |
|
T4 |
3 |
| false |
108 |
1 |
|
T1 |
4 |
|
T4 |
3 |
|
T138 |
5 |
| true |
5642 |
1 |
|
T1 |
53 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1292 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T13 |
1 |
| others[1] |
1245 |
1 |
|
T1 |
21 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
1236 |
1 |
|
T1 |
28 |
|
T10 |
1 |
|
T4 |
4 |
| others[3] |
2049 |
1 |
|
T1 |
25 |
|
T4 |
7 |
|
T82 |
1 |
| false |
624 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T138 |
8 |
| true |
330 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8 |
1 |
|
T69 |
1 |
|
T99 |
1 |
|
T174 |
1 |
| others[1] |
13 |
1 |
|
T33 |
1 |
|
T108 |
1 |
|
T116 |
2 |
| others[2] |
2 |
1 |
|
T337 |
1 |
|
T338 |
1 |
|
- |
- |
| others[3] |
5 |
1 |
|
T24 |
1 |
|
T339 |
1 |
|
T340 |
1 |
| false |
4 |
1 |
|
T83 |
1 |
|
T341 |
1 |
|
T342 |
1 |
| true |
60 |
1 |
|
T69 |
1 |
|
T123 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T343 |
1 |
|
T344 |
1 |
|
T345 |
1 |
| others[1] |
3 |
1 |
|
T346 |
1 |
|
T347 |
1 |
|
T348 |
1 |
| others[2] |
2 |
1 |
|
T90 |
1 |
|
T349 |
1 |
|
- |
- |
| others[3] |
2 |
1 |
|
T89 |
1 |
|
T350 |
1 |
|
- |
- |
| false |
12 |
1 |
|
T44 |
1 |
|
T351 |
1 |
|
T352 |
1 |
| true |
26 |
1 |
|
T26 |
1 |
|
T56 |
1 |
|
T226 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T352 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
1 |
1 |
|
T353 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
2 |
1 |
|
T345 |
1 |
|
T354 |
1 |
|
- |
- |
| others[3] |
3 |
1 |
|
T56 |
1 |
|
T355 |
1 |
|
T356 |
1 |
| false |
16 |
1 |
|
T26 |
1 |
|
T250 |
1 |
|
T90 |
1 |
| true |
25 |
1 |
|
T44 |
1 |
|
T226 |
1 |
|
T89 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |