Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10142 |
1 |
|
T1 |
16 |
|
T4 |
4 |
|
T20 |
2 |
| others[1] |
810 |
1 |
|
T1 |
17 |
|
T4 |
2 |
|
T15 |
1 |
| others[2] |
788 |
1 |
|
T1 |
28 |
|
T138 |
18 |
|
T30 |
2 |
| others[3] |
1340 |
1 |
|
T1 |
31 |
|
T2 |
1 |
|
T10 |
1 |
| false |
404 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T138 |
7 |
| true |
383 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2423 |
1 |
|
T1 |
7 |
|
T10 |
1 |
|
T4 |
1 |
| others[1] |
2394 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T138 |
12 |
| others[2] |
2423 |
1 |
|
T1 |
11 |
|
T4 |
5 |
|
T138 |
14 |
| others[3] |
3973 |
1 |
|
T1 |
18 |
|
T4 |
7 |
|
T5 |
1 |
| false |
1217 |
1 |
|
T1 |
5 |
|
T16 |
1 |
|
T4 |
2 |
| true |
1437 |
1 |
|
T1 |
49 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9571 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T14 |
1 |
| others[1] |
255 |
1 |
|
T1 |
6 |
|
T16 |
1 |
|
T4 |
1 |
| others[2] |
257 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T42 |
1 |
| others[3] |
442 |
1 |
|
T1 |
22 |
|
T4 |
4 |
|
T12 |
1 |
| false |
124 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T138 |
4 |
| true |
3218 |
1 |
|
T1 |
49 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9812 |
1 |
|
T1 |
13 |
|
T10 |
1 |
|
T4 |
7 |
| others[1] |
431 |
1 |
|
T1 |
14 |
|
T4 |
1 |
|
T15 |
1 |
| others[2] |
466 |
1 |
|
T1 |
12 |
|
T6 |
1 |
|
T16 |
1 |
| others[3] |
746 |
1 |
|
T1 |
10 |
|
T4 |
10 |
|
T42 |
1 |
| false |
247 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T138 |
6 |
| true |
2165 |
1 |
|
T1 |
46 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9572 |
1 |
|
T1 |
13 |
|
T4 |
2 |
|
T17 |
1 |
| others[1] |
280 |
1 |
|
T1 |
11 |
|
T10 |
1 |
|
T4 |
4 |
| others[2] |
239 |
1 |
|
T1 |
8 |
|
T5 |
1 |
|
T138 |
8 |
| others[3] |
433 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T42 |
1 |
| false |
126 |
1 |
|
T4 |
2 |
|
T84 |
1 |
|
T138 |
7 |
| true |
3217 |
1 |
|
T1 |
51 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9601 |
1 |
|
T1 |
10 |
|
T10 |
1 |
|
T4 |
2 |
| others[1] |
236 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T42 |
1 |
| others[2] |
239 |
1 |
|
T1 |
13 |
|
T4 |
1 |
|
T138 |
10 |
| others[3] |
400 |
1 |
|
T1 |
11 |
|
T16 |
1 |
|
T4 |
1 |
| false |
126 |
1 |
|
T1 |
10 |
|
T138 |
7 |
|
T57 |
1 |
| true |
3265 |
1 |
|
T1 |
49 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10162 |
1 |
|
T1 |
21 |
|
T10 |
1 |
|
T4 |
7 |
| others[1] |
791 |
1 |
|
T1 |
19 |
|
T13 |
1 |
|
T54 |
1 |
| others[2] |
795 |
1 |
|
T1 |
21 |
|
T2 |
1 |
|
T4 |
2 |
| others[3] |
1329 |
1 |
|
T1 |
29 |
|
T16 |
1 |
|
T4 |
1 |
| false |
401 |
1 |
|
T1 |
11 |
|
T11 |
1 |
|
T138 |
3 |
| true |
389 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T4 |
10 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10168 |
1 |
|
T1 |
20 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
784 |
1 |
|
T1 |
18 |
|
T2 |
1 |
|
T4 |
3 |
| others[2] |
820 |
1 |
|
T1 |
17 |
|
T4 |
5 |
|
T13 |
1 |
| others[3] |
1249 |
1 |
|
T1 |
36 |
|
T4 |
2 |
|
T138 |
26 |
| false |
423 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T12 |
1 |
| true |
397 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2299 |
1 |
|
T1 |
10 |
|
T4 |
3 |
|
T20 |
1 |
| others[1] |
2385 |
1 |
|
T1 |
8 |
|
T4 |
4 |
|
T84 |
1 |
| others[2] |
2409 |
1 |
|
T1 |
9 |
|
T4 |
5 |
|
T54 |
1 |
| others[3] |
4043 |
1 |
|
T1 |
23 |
|
T10 |
1 |
|
T16 |
1 |
| false |
1256 |
1 |
|
T1 |
7 |
|
T42 |
1 |
|
T138 |
6 |
| true |
1449 |
1 |
|
T1 |
44 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9580 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T20 |
2 |
| others[1] |
226 |
1 |
|
T1 |
7 |
|
T4 |
2 |
|
T17 |
1 |
| others[2] |
259 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T14 |
1 |
| others[3] |
433 |
1 |
|
T1 |
18 |
|
T42 |
1 |
|
T54 |
1 |
| false |
136 |
1 |
|
T1 |
9 |
|
T11 |
2 |
|
T138 |
5 |
| true |
3207 |
1 |
|
T1 |
49 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9767 |
1 |
|
T1 |
10 |
|
T4 |
5 |
|
T20 |
2 |
| others[1] |
467 |
1 |
|
T1 |
9 |
|
T4 |
4 |
|
T11 |
1 |
| others[2] |
443 |
1 |
|
T1 |
7 |
|
T6 |
1 |
|
T4 |
2 |
| others[3] |
794 |
1 |
|
T1 |
19 |
|
T2 |
1 |
|
T10 |
1 |
| false |
263 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T33 |
1 |
| true |
2107 |
1 |
|
T1 |
52 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9567 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T20 |
2 |
| others[1] |
255 |
1 |
|
T1 |
13 |
|
T15 |
1 |
|
T13 |
1 |
| others[2] |
264 |
1 |
|
T1 |
9 |
|
T4 |
4 |
|
T84 |
1 |
| others[3] |
415 |
1 |
|
T1 |
13 |
|
T4 |
2 |
|
T93 |
1 |
| false |
144 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T17 |
1 |
| true |
3196 |
1 |
|
T1 |
48 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9559 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T17 |
1 |
| others[1] |
237 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T11 |
3 |
| others[2] |
264 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T12 |
1 |
| others[3] |
385 |
1 |
|
T1 |
21 |
|
T11 |
2 |
|
T13 |
1 |
| false |
149 |
1 |
|
T1 |
7 |
|
T4 |
3 |
|
T93 |
1 |
| true |
3247 |
1 |
|
T1 |
45 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10077 |
1 |
|
T1 |
17 |
|
T10 |
1 |
|
T4 |
3 |
| others[1] |
800 |
1 |
|
T1 |
15 |
|
T4 |
4 |
|
T54 |
1 |
| others[2] |
792 |
1 |
|
T1 |
18 |
|
T2 |
1 |
|
T4 |
3 |
| others[3] |
1380 |
1 |
|
T1 |
43 |
|
T4 |
3 |
|
T138 |
40 |
| false |
399 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T5 |
1 |
| true |
393 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10100 |
1 |
|
T1 |
18 |
|
T4 |
2 |
|
T20 |
2 |
| others[1] |
845 |
1 |
|
T1 |
26 |
|
T4 |
2 |
|
T138 |
23 |
| others[2] |
766 |
1 |
|
T1 |
19 |
|
T82 |
1 |
|
T84 |
1 |
| others[3] |
1310 |
1 |
|
T1 |
25 |
|
T2 |
1 |
|
T4 |
3 |
| false |
413 |
1 |
|
T1 |
13 |
|
T4 |
2 |
|
T5 |
1 |
| true |
407 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2354 |
1 |
|
T1 |
9 |
|
T4 |
3 |
|
T42 |
1 |
| others[1] |
2371 |
1 |
|
T1 |
12 |
|
T16 |
1 |
|
T4 |
1 |
| others[2] |
2386 |
1 |
|
T1 |
8 |
|
T4 |
7 |
|
T54 |
1 |
| others[3] |
4108 |
1 |
|
T1 |
11 |
|
T10 |
1 |
|
T4 |
5 |
| false |
1227 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T17 |
1 |
| true |
1395 |
1 |
|
T1 |
56 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9585 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T17 |
1 |
| others[1] |
241 |
1 |
|
T1 |
7 |
|
T4 |
4 |
|
T138 |
10 |
| others[2] |
268 |
1 |
|
T1 |
11 |
|
T84 |
1 |
|
T138 |
6 |
| others[3] |
415 |
1 |
|
T1 |
19 |
|
T10 |
1 |
|
T15 |
1 |
| false |
146 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T54 |
1 |
| true |
3186 |
1 |
|
T1 |
48 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9786 |
1 |
|
T1 |
14 |
|
T6 |
1 |
|
T4 |
2 |
| others[1] |
435 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
1 |
| others[2] |
481 |
1 |
|
T1 |
8 |
|
T10 |
1 |
|
T4 |
4 |
| others[3] |
777 |
1 |
|
T1 |
24 |
|
T16 |
1 |
|
T4 |
7 |
| false |
231 |
1 |
|
T1 |
6 |
|
T4 |
3 |
|
T138 |
6 |
| true |
2131 |
1 |
|
T1 |
41 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9563 |
1 |
|
T1 |
10 |
|
T10 |
1 |
|
T14 |
1 |
| others[1] |
254 |
1 |
|
T1 |
7 |
|
T4 |
2 |
|
T42 |
1 |
| others[2] |
255 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T17 |
1 |
| others[3] |
429 |
1 |
|
T1 |
10 |
|
T4 |
3 |
|
T15 |
1 |
| false |
142 |
1 |
|
T1 |
4 |
|
T138 |
6 |
|
T57 |
1 |
| true |
3198 |
1 |
|
T1 |
59 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9573 |
1 |
|
T1 |
8 |
|
T20 |
2 |
|
T42 |
1 |
| others[1] |
245 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T84 |
1 |
| others[2] |
241 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T11 |
1 |
| others[3] |
410 |
1 |
|
T1 |
20 |
|
T6 |
1 |
|
T10 |
1 |
| false |
118 |
1 |
|
T1 |
5 |
|
T138 |
6 |
|
T139 |
6 |
| true |
3254 |
1 |
|
T1 |
48 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10149 |
1 |
|
T1 |
18 |
|
T4 |
2 |
|
T20 |
2 |
| others[1] |
830 |
1 |
|
T1 |
22 |
|
T4 |
2 |
|
T12 |
1 |
| others[2] |
766 |
1 |
|
T1 |
22 |
|
T3 |
1 |
|
T4 |
2 |
| others[3] |
1309 |
1 |
|
T1 |
30 |
|
T10 |
1 |
|
T5 |
1 |
| false |
413 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T4 |
1 |
| true |
374 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T4 |
10 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10126 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T20 |
2 |
| others[1] |
797 |
1 |
|
T1 |
10 |
|
T10 |
1 |
|
T17 |
1 |
| others[2] |
777 |
1 |
|
T1 |
23 |
|
T4 |
3 |
|
T12 |
1 |
| others[3] |
1321 |
1 |
|
T1 |
32 |
|
T2 |
1 |
|
T3 |
1 |
| false |
422 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T5 |
1 |
| true |
398 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T4 |
9 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2323 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T54 |
1 |
| others[1] |
2394 |
1 |
|
T1 |
6 |
|
T4 |
6 |
|
T138 |
13 |
| others[2] |
2416 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
4048 |
1 |
|
T1 |
18 |
|
T4 |
7 |
|
T20 |
2 |
| false |
1243 |
1 |
|
T1 |
6 |
|
T10 |
1 |
|
T4 |
1 |
| true |
1417 |
1 |
|
T1 |
54 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9550 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T20 |
2 |
| others[1] |
281 |
1 |
|
T1 |
11 |
|
T10 |
1 |
|
T93 |
1 |
| others[2] |
254 |
1 |
|
T1 |
6 |
|
T4 |
2 |
|
T15 |
1 |
| others[3] |
444 |
1 |
|
T1 |
18 |
|
T4 |
4 |
|
T13 |
1 |
| false |
124 |
1 |
|
T1 |
5 |
|
T138 |
3 |
|
T61 |
1 |
| true |
3188 |
1 |
|
T1 |
52 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9785 |
1 |
|
T1 |
10 |
|
T16 |
1 |
|
T4 |
5 |
| others[1] |
463 |
1 |
|
T1 |
11 |
|
T10 |
1 |
|
T4 |
4 |
| others[2] |
463 |
1 |
|
T1 |
9 |
|
T3 |
1 |
|
T4 |
1 |
| others[3] |
753 |
1 |
|
T1 |
14 |
|
T4 |
6 |
|
T14 |
1 |
| false |
216 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T138 |
3 |
| true |
2161 |
1 |
|
T1 |
51 |
|
T2 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9592 |
1 |
|
T1 |
9 |
|
T20 |
2 |
|
T12 |
1 |
| others[1] |
236 |
1 |
|
T1 |
12 |
|
T6 |
1 |
|
T4 |
2 |
| others[2] |
243 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T5 |
1 |
| others[3] |
414 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T84 |
1 |
| false |
145 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T13 |
1 |
| true |
3211 |
1 |
|
T1 |
50 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9551 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T20 |
2 |
| others[1] |
246 |
1 |
|
T1 |
9 |
|
T4 |
3 |
|
T138 |
11 |
| others[2] |
279 |
1 |
|
T1 |
9 |
|
T10 |
1 |
|
T5 |
1 |
| others[3] |
402 |
1 |
|
T1 |
16 |
|
T4 |
4 |
|
T11 |
1 |
| false |
110 |
1 |
|
T1 |
2 |
|
T17 |
1 |
|
T138 |
2 |
| true |
3253 |
1 |
|
T1 |
60 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10131 |
1 |
|
T1 |
19 |
|
T16 |
1 |
|
T4 |
1 |
| others[1] |
795 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T138 |
18 |
| others[2] |
765 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T54 |
1 |
| others[3] |
1350 |
1 |
|
T1 |
42 |
|
T2 |
1 |
|
T4 |
4 |
| false |
405 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T11 |
1 |
| true |
395 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10116 |
1 |
|
T1 |
20 |
|
T3 |
1 |
|
T4 |
1 |
| others[1] |
778 |
1 |
|
T1 |
27 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
810 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T11 |
2 |
| others[3] |
1310 |
1 |
|
T1 |
30 |
|
T4 |
1 |
|
T11 |
1 |
| false |
415 |
1 |
|
T1 |
7 |
|
T2 |
1 |
|
T4 |
1 |
| true |
412 |
1 |
|
T6 |
1 |
|
T10 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2413 |
1 |
|
T1 |
14 |
|
T16 |
1 |
|
T4 |
3 |
| others[1] |
2403 |
1 |
|
T1 |
14 |
|
T4 |
3 |
|
T84 |
1 |
| others[2] |
2392 |
1 |
|
T1 |
5 |
|
T4 |
4 |
|
T5 |
1 |
| others[3] |
3968 |
1 |
|
T1 |
18 |
|
T10 |
1 |
|
T4 |
3 |
| false |
1258 |
1 |
|
T1 |
3 |
|
T4 |
4 |
|
T138 |
4 |
| true |
1407 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9561 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T20 |
2 |
| others[1] |
276 |
1 |
|
T1 |
10 |
|
T4 |
3 |
|
T11 |
1 |
| others[2] |
258 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T11 |
2 |
| others[3] |
451 |
1 |
|
T1 |
18 |
|
T16 |
1 |
|
T15 |
1 |
| false |
116 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T138 |
3 |
| true |
3179 |
1 |
|
T1 |
48 |
|
T2 |
1 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |