Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9804 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T82 |
1 |
| others[1] |
475 |
1 |
|
T1 |
12 |
|
T10 |
1 |
|
T4 |
6 |
| others[2] |
472 |
1 |
|
T1 |
4 |
|
T16 |
1 |
|
T4 |
2 |
| others[3] |
732 |
1 |
|
T1 |
15 |
|
T2 |
1 |
|
T4 |
7 |
| false |
246 |
1 |
|
T1 |
4 |
|
T5 |
1 |
|
T138 |
1 |
| true |
2112 |
1 |
|
T1 |
57 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9589 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
234 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T138 |
11 |
| others[2] |
245 |
1 |
|
T1 |
10 |
|
T42 |
1 |
|
T54 |
1 |
| others[3] |
409 |
1 |
|
T1 |
21 |
|
T4 |
4 |
|
T17 |
1 |
| false |
121 |
1 |
|
T1 |
2 |
|
T4 |
2 |
|
T138 |
2 |
| true |
3243 |
1 |
|
T1 |
53 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9556 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T5 |
1 |
| others[1] |
246 |
1 |
|
T1 |
10 |
|
T16 |
1 |
|
T4 |
2 |
| others[2] |
267 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T11 |
1 |
| others[3] |
409 |
1 |
|
T1 |
15 |
|
T10 |
1 |
|
T4 |
4 |
| false |
118 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T11 |
2 |
| true |
3245 |
1 |
|
T1 |
46 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10103 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
823 |
1 |
|
T1 |
20 |
|
T4 |
1 |
|
T11 |
1 |
| others[2] |
867 |
1 |
|
T1 |
24 |
|
T2 |
1 |
|
T4 |
1 |
| others[3] |
1267 |
1 |
|
T1 |
29 |
|
T4 |
1 |
|
T12 |
1 |
| false |
379 |
1 |
|
T1 |
12 |
|
T13 |
1 |
|
T138 |
9 |
| true |
402 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10070 |
1 |
|
T1 |
21 |
|
T4 |
2 |
|
T82 |
1 |
| others[1] |
821 |
1 |
|
T1 |
15 |
|
T12 |
1 |
|
T138 |
22 |
| others[2] |
780 |
1 |
|
T1 |
22 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
1369 |
1 |
|
T1 |
34 |
|
T2 |
1 |
|
T4 |
7 |
| false |
399 |
1 |
|
T1 |
9 |
|
T54 |
1 |
|
T138 |
7 |
| true |
402 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2395 |
1 |
|
T1 |
14 |
|
T4 |
1 |
|
T54 |
1 |
| others[1] |
2357 |
1 |
|
T1 |
6 |
|
T4 |
3 |
|
T5 |
1 |
| others[2] |
2439 |
1 |
|
T1 |
10 |
|
T10 |
1 |
|
T16 |
1 |
| others[3] |
4031 |
1 |
|
T1 |
14 |
|
T4 |
4 |
|
T20 |
1 |
| false |
1155 |
1 |
|
T1 |
7 |
|
T54 |
1 |
|
T138 |
8 |
| true |
1464 |
1 |
|
T1 |
50 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9602 |
1 |
|
T1 |
13 |
|
T4 |
2 |
|
T20 |
2 |
| others[1] |
260 |
1 |
|
T1 |
10 |
|
T54 |
1 |
|
T93 |
1 |
| others[2] |
244 |
1 |
|
T1 |
16 |
|
T6 |
1 |
|
T4 |
2 |
| others[3] |
435 |
1 |
|
T1 |
12 |
|
T4 |
3 |
|
T11 |
1 |
| false |
132 |
1 |
|
T1 |
9 |
|
T138 |
4 |
|
T139 |
5 |
| true |
3168 |
1 |
|
T1 |
41 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9783 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T6 |
1 |
| others[1] |
469 |
1 |
|
T1 |
10 |
|
T4 |
3 |
|
T14 |
1 |
| others[2] |
481 |
1 |
|
T1 |
7 |
|
T10 |
1 |
|
T4 |
3 |
| others[3] |
778 |
1 |
|
T1 |
18 |
|
T4 |
8 |
|
T42 |
1 |
| false |
236 |
1 |
|
T1 |
4 |
|
T16 |
1 |
|
T4 |
1 |
| true |
2094 |
1 |
|
T1 |
48 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9569 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T15 |
1 |
| others[1] |
240 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T14 |
1 |
| others[2] |
261 |
1 |
|
T1 |
4 |
|
T6 |
1 |
|
T16 |
1 |
| others[3] |
431 |
1 |
|
T1 |
20 |
|
T4 |
3 |
|
T5 |
1 |
| false |
121 |
1 |
|
T1 |
5 |
|
T138 |
3 |
|
T130 |
1 |
| true |
3219 |
1 |
|
T1 |
52 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9565 |
1 |
|
T1 |
15 |
|
T10 |
1 |
|
T20 |
2 |
| others[1] |
249 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T12 |
1 |
| others[2] |
230 |
1 |
|
T1 |
6 |
|
T4 |
5 |
|
T5 |
1 |
| others[3] |
406 |
1 |
|
T1 |
13 |
|
T6 |
1 |
|
T4 |
1 |
| false |
130 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T11 |
3 |
| true |
3261 |
1 |
|
T1 |
53 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10093 |
1 |
|
T1 |
18 |
|
T4 |
4 |
|
T20 |
2 |
| others[1] |
800 |
1 |
|
T1 |
19 |
|
T4 |
3 |
|
T5 |
1 |
| others[2] |
826 |
1 |
|
T1 |
24 |
|
T4 |
2 |
|
T83 |
1 |
| others[3] |
1315 |
1 |
|
T1 |
32 |
|
T2 |
1 |
|
T4 |
2 |
| false |
396 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T138 |
7 |
| true |
411 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10087 |
1 |
|
T1 |
17 |
|
T4 |
3 |
|
T20 |
2 |
| others[1] |
796 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T12 |
1 |
| others[2] |
840 |
1 |
|
T1 |
22 |
|
T4 |
2 |
|
T13 |
1 |
| others[3] |
1319 |
1 |
|
T1 |
34 |
|
T2 |
1 |
|
T4 |
4 |
| false |
400 |
1 |
|
T1 |
12 |
|
T93 |
1 |
|
T138 |
11 |
| true |
399 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2359 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T20 |
1 |
| others[1] |
2357 |
1 |
|
T1 |
5 |
|
T4 |
3 |
|
T5 |
1 |
| others[2] |
2498 |
1 |
|
T1 |
14 |
|
T10 |
1 |
|
T4 |
1 |
| others[3] |
3996 |
1 |
|
T1 |
16 |
|
T4 |
10 |
|
T20 |
1 |
| false |
1198 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T54 |
1 |
| true |
1433 |
1 |
|
T1 |
51 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9574 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T15 |
1 |
| others[1] |
280 |
1 |
|
T1 |
8 |
|
T6 |
1 |
|
T4 |
1 |
| others[2] |
247 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T5 |
1 |
| others[3] |
417 |
1 |
|
T1 |
16 |
|
T16 |
1 |
|
T84 |
1 |
| false |
115 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T54 |
1 |
| true |
3208 |
1 |
|
T1 |
54 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9744 |
1 |
|
T1 |
13 |
|
T4 |
3 |
|
T82 |
1 |
| others[1] |
446 |
1 |
|
T1 |
9 |
|
T6 |
1 |
|
T4 |
3 |
| others[2] |
472 |
1 |
|
T1 |
8 |
|
T4 |
5 |
|
T5 |
1 |
| others[3] |
746 |
1 |
|
T1 |
13 |
|
T3 |
1 |
|
T10 |
1 |
| false |
234 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T15 |
1 |
| true |
2199 |
1 |
|
T1 |
52 |
|
T2 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9582 |
1 |
|
T1 |
9 |
|
T16 |
1 |
|
T4 |
2 |
| others[1] |
288 |
1 |
|
T1 |
11 |
|
T10 |
1 |
|
T4 |
3 |
| others[2] |
256 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T138 |
8 |
| others[3] |
414 |
1 |
|
T1 |
22 |
|
T4 |
3 |
|
T17 |
1 |
| false |
122 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T138 |
8 |
| true |
3179 |
1 |
|
T1 |
44 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9612 |
1 |
|
T1 |
16 |
|
T6 |
1 |
|
T4 |
1 |
| others[1] |
235 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T54 |
1 |
| others[2] |
243 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T11 |
1 |
| others[3] |
389 |
1 |
|
T1 |
14 |
|
T4 |
3 |
|
T11 |
1 |
| false |
128 |
1 |
|
T1 |
6 |
|
T4 |
2 |
|
T12 |
1 |
| true |
3234 |
1 |
|
T1 |
42 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10123 |
1 |
|
T1 |
19 |
|
T2 |
1 |
|
T4 |
2 |
| others[1] |
807 |
1 |
|
T1 |
26 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
803 |
1 |
|
T1 |
21 |
|
T10 |
1 |
|
T13 |
1 |
| others[3] |
1323 |
1 |
|
T1 |
24 |
|
T4 |
5 |
|
T54 |
1 |
| false |
406 |
1 |
|
T1 |
11 |
|
T138 |
9 |
|
T30 |
3 |
| true |
379 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10102 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T20 |
2 |
| others[1] |
799 |
1 |
|
T1 |
23 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
791 |
1 |
|
T1 |
15 |
|
T2 |
1 |
|
T4 |
1 |
| others[3] |
1357 |
1 |
|
T1 |
39 |
|
T4 |
5 |
|
T12 |
1 |
| false |
382 |
1 |
|
T1 |
9 |
|
T54 |
1 |
|
T138 |
9 |
| true |
410 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2435 |
1 |
|
T1 |
11 |
|
T4 |
4 |
|
T5 |
1 |
| others[1] |
2400 |
1 |
|
T1 |
13 |
|
T10 |
1 |
|
T4 |
8 |
| others[2] |
2292 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T138 |
11 |
| others[3] |
3942 |
1 |
|
T1 |
15 |
|
T16 |
1 |
|
T4 |
4 |
| false |
1301 |
1 |
|
T1 |
5 |
|
T138 |
5 |
|
T30 |
4 |
| true |
1471 |
1 |
|
T1 |
48 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9567 |
1 |
|
T1 |
9 |
|
T17 |
1 |
|
T14 |
1 |
| others[1] |
265 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
248 |
1 |
|
T1 |
13 |
|
T4 |
1 |
|
T11 |
1 |
| others[3] |
460 |
1 |
|
T1 |
17 |
|
T10 |
1 |
|
T16 |
1 |
| false |
132 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T138 |
4 |
| true |
3169 |
1 |
|
T1 |
49 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9753 |
1 |
|
T1 |
9 |
|
T4 |
4 |
|
T5 |
1 |
| others[1] |
434 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T6 |
1 |
| others[2] |
498 |
1 |
|
T1 |
11 |
|
T4 |
4 |
|
T12 |
1 |
| others[3] |
786 |
1 |
|
T1 |
15 |
|
T10 |
1 |
|
T4 |
4 |
| false |
249 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T11 |
1 |
| true |
2121 |
1 |
|
T1 |
46 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9568 |
1 |
|
T1 |
7 |
|
T4 |
3 |
|
T20 |
2 |
| others[1] |
252 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T138 |
8 |
| others[2] |
229 |
1 |
|
T1 |
10 |
|
T84 |
1 |
|
T93 |
1 |
| others[3] |
446 |
1 |
|
T1 |
16 |
|
T4 |
2 |
|
T13 |
1 |
| false |
145 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T14 |
1 |
| true |
3201 |
1 |
|
T1 |
52 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9556 |
1 |
|
T1 |
6 |
|
T20 |
2 |
|
T11 |
1 |
| others[1] |
268 |
1 |
|
T1 |
13 |
|
T11 |
1 |
|
T93 |
1 |
| others[2] |
248 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
377 |
1 |
|
T1 |
15 |
|
T16 |
1 |
|
T4 |
3 |
| false |
130 |
1 |
|
T1 |
7 |
|
T4 |
2 |
|
T11 |
2 |
| true |
3262 |
1 |
|
T1 |
53 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10142 |
1 |
|
T1 |
16 |
|
T10 |
1 |
|
T4 |
2 |
| others[1] |
780 |
1 |
|
T1 |
22 |
|
T3 |
1 |
|
T4 |
2 |
| others[2] |
771 |
1 |
|
T1 |
23 |
|
T4 |
2 |
|
T5 |
1 |
| others[3] |
1331 |
1 |
|
T1 |
31 |
|
T4 |
3 |
|
T13 |
1 |
| false |
430 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T138 |
13 |
| true |
387 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T4 |
8 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |