Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	191542	1		T1	100		T2	15		T6	20
auto[FlashEraseBank]	223588	1		T1	1197		T2	1		T10	2

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	231450	1		T1	618		T2	8		T6	20
auto[FlashOpProgram]	164201	1		T1	634		T2	4		T10	1
auto[FlashOpErase]	15479	1		T1	45		T2	4		T4	4
auto[FlashOpInvalid]	4000	1		T129	200		T159	200		T154	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	231450	1		T1	618		T2	8		T6	20
op[FlashOpProgram]	164201	1		T1	634		T2	4		T10	1
op[FlashOpErase]	15479	1		T1	45		T2	4		T4	4
read_erase_read	796	1		T1	7		T2	2		T12	4
read_prog_read	506	1		T1	7		T2	1		T16	5

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	292833	1		T1	98		T2	16		T6	20
auto[FlashPartInfo]	119308	1		T1	1198		T16	517		T17	244
auto[FlashPartInfo1]	748	1		T16	1		T17	3		T15	17
auto[FlashPartInfo2]	2241	1		T1	1		T16	10		T17	13

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	169117	1		T1	42		T2	8		T6	20
auto[FlashPartData]	auto[FlashOpProgram]	116202	1		T1	25		T2	4		T10	1
auto[FlashPartData]	auto[FlashOpErase]	3586	1		T1	31		T2	4		T4	4
auto[FlashPartData]	auto[FlashOpInvalid]	3928	1		T129	196		T159	194		T154	196
auto[FlashPartInfo]	auto[FlashOpRead]	60271	1		T1	576		T16	279		T17	244
auto[FlashPartInfo]	auto[FlashOpProgram]	47159	1		T1	609		T16	238		T44	352
auto[FlashPartInfo]	auto[FlashOpErase]	11816	1		T1	13		T44	8		T20	3
auto[FlashPartInfo]	auto[FlashOpInvalid]	62	1		T129	2		T159	6		T154	2
auto[FlashPartInfo1]	auto[FlashOpRead]	579	1		T16	1		T17	3		T15	17
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T129	1		T162	32		T142	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T129	1		T148	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T129	2		T148	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1483	1		T16	1		T17	13		T15	30
auto[FlashPartInfo2]	auto[FlashOpProgram]	677	1		T16	9		T11	2		T54	1
auto[FlashPartInfo2]	auto[FlashOpErase]	75	1		T1	1		T79	9		T154	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T154	2		T360	2		T361	2