Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.10	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	5	27	84.38

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	5	27	84.38	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29639	1		T1	12		T2	32		T12	20
auto[1]	12	1		T78	1		T166	6		T306	1
auto[2]	17	1		T168	4		T307	2		T308	3
auto[3]	40	1		T40	1		T80	1		T41	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7424	1		T1	3		T2	8		T12	5
evic_idx[1]	7422	1		T1	3		T2	8		T12	5
evic_idx[2]	7434	1		T1	3		T2	8		T12	5
evic_idx[3]	7428	1		T1	3		T2	8		T12	5

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28842	1		T1	8		T2	12		T45	296
evic_op[2]	286	1		T1	4		T2	16		T101	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	5	27	84.38	5

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	*	[auto[2]]	--	--	2

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1] , evic_idx[2] , evic_idx[3]]	[evic_op[2]]	[auto[2]]	--	--	3

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7202	1		T1	2		T2	3		T45	74
evic_idx[0]	evic_op[1]	auto[1]	1	1		T166	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	4	1		T309	1		T310	3		-	-
evic_idx[0]	evic_op[2]	auto[0]	64	1		T1	1		T2	4		T101	4
evic_idx[0]	evic_op[2]	auto[1]	1	1		T306	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	7	1		T41	1		T205	1		T311	1
evic_idx[1]	evic_op[1]	auto[0]	7203	1		T1	2		T2	3		T45	74
evic_idx[1]	evic_op[1]	auto[1]	1	1		T166	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	1	1		T308	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	5	1		T309	1		T310	3		T312	1
evic_idx[1]	evic_op[2]	auto[0]	63	1		T1	1		T2	4		T101	4
evic_idx[1]	evic_op[2]	auto[1]	1	1		T313	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	3	1		T314	1		T205	1		T315	1
evic_idx[2]	evic_op[1]	auto[0]	7204	1		T1	2		T2	3		T45	74
evic_idx[2]	evic_op[1]	auto[1]	2	1		T166	2		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	2	1		T307	1		T308	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	5	1		T309	1		T310	3		T312	1
evic_idx[2]	evic_op[2]	auto[0]	67	1		T1	1		T2	4		T101	4
evic_idx[2]	evic_op[2]	auto[1]	3	1		T78	1		T316	1		T313	1
evic_idx[2]	evic_op[2]	auto[3]	6	1		T80	1		T314	1		T205	1
evic_idx[3]	evic_op[1]	auto[0]	7203	1		T1	2		T2	3		T45	74
evic_idx[3]	evic_op[1]	auto[1]	2	1		T166	2		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	2	1		T307	1		T308	1		-	-
evic_idx[3]	evic_op[1]	auto[3]	5	1		T309	2		T310	3		-	-
evic_idx[3]	evic_op[2]	auto[0]	65	1		T1	1		T2	4		T101	4
evic_idx[3]	evic_op[2]	auto[1]	1	1		T313	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	5	1		T40	1		T205	1		T317	1