Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	14661	1		T100	1217		T300	1651		T301	7329
rd_lvl[2]	49888	1		T100	1858		T300	1735		T302	5702
rd_lvl[3]	11906	1		T100	661		T300	504		T303	1471
rd_lvl[4]	31759	1		T60	2071		T100	1261		T304	2301
rd_lvl[5]	20224	1		T60	997		T100	353		T304	891
rd_lvl[6]	16433	1		T100	851		T271	625		T300	658
rd_lvl[7]	10214	1		T100	219		T195	2		T300	245
rd_lvl[8]	13135	1		T100	203		T195	2		T271	68
rd_lvl[9]	6943	1		T100	968		T300	581		T277	612
rd_lvl[10]	6984	1		T15	523		T100	200		T300	122
rd_lvl[11]	9195	1		T15	421		T100	1579		T271	68
rd_lvl[12]	4988	1		T5	516		T300	1		T277	28
rd_lvl[13]	7130	1		T5	304		T15	25		T102	554
rd_lvl[14]	3456	1		T100	43		T102	405		T270	605
rd_lvl[15]	4415	1		T14	565		T81	633		T305	592