Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	287763	1		T1	2		T2	2		T3	1
all_pins[1]	287763	1		T1	2		T2	2		T3	1
all_pins[2]	287763	1		T1	2		T2	2		T3	1
all_pins[3]	287763	1		T1	2		T2	2		T3	1
all_pins[4]	287763	1		T1	2		T2	2		T3	1
all_pins[5]	287763	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1426712	1		T1	12		T2	12		T3	6
values[0x1]	299866	1		T5	1640		T14	3035		T15	1938
transitions[0x0=>0x1]	269274	1		T5	1640		T14	2055		T15	1938
transitions[0x1=>0x0]	269264	1		T5	1640		T14	2055		T15	1938

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	287610	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	153	1		T256	6		T257	5		T258	6
all_pins[0]	transitions[0x0=>0x1]	70	1		T256	5		T257	4		T258	1
all_pins[0]	transitions[0x1=>0x0]	88	1		T256	1		T257	2		T258	1
all_pins[1]	values[0x0]	287592	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	171	1		T256	2		T257	3		T258	6
all_pins[1]	transitions[0x0=>0x1]	143	1		T256	1		T258	6		T296	3
all_pins[1]	transitions[0x1=>0x0]	2924	1		T14	490		T81	541		T305	241
all_pins[2]	values[0x0]	284811	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	2952	1		T14	490		T81	541		T305	241
all_pins[2]	transitions[0x0=>0x1]	34	1		T256	1		T257	2		T297	1
all_pins[2]	transitions[0x1=>0x0]	211751	1		T5	820		T14	565		T15	969
all_pins[3]	values[0x0]	73094	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	214669	1		T5	820		T14	1055		T15	969
all_pins[3]	transitions[0x0=>0x1]	187157	1		T5	820		T14	565		T15	969
all_pins[3]	transitions[0x1=>0x0]	54342	1		T5	820		T14	1000		T15	969
all_pins[4]	values[0x0]	205909	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	81854	1		T5	820		T14	1490		T15	969
all_pins[4]	transitions[0x0=>0x1]	81841	1		T5	820		T14	1490		T15	969
all_pins[4]	transitions[0x1=>0x0]	54	1		T256	4		T257	3		T258	1
all_pins[5]	values[0x0]	287696	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	67	1		T256	4		T257	3		T258	1
all_pins[5]	transitions[0x0=>0x1]	29	1		T256	1		T257	2		T299	1
all_pins[5]	transitions[0x1=>0x0]	105	1		T256	2		T257	3		T258	5