Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmRdFifoRptrCheck_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmRdFifoWptrCheck_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	345337277	0	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	345337277	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	345337277	0	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	345337277	0	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	345337277	0	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	345337277	0	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	345337277	0	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	345337277	0	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	345337277	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	345337277	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	345337277	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	345337277	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	345337277	0	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	345337277	0	0	874
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	345337277	0	0	874
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	345337277	0	0	874
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	345337277	0	0	874
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	345337277	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	345337277	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	345337277	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	345337277	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	345337277	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	345337277	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	345337277	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	345337277	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	879	879	0	0
tb.dut.FlashAddrKnown_A	0	0	345337277	248307906	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	345337277	344641816	0	0
tb.dut.FlashKnownO_A	0	0	345337277	344641816	0	0
tb.dut.FlashProgKnown_A	0	0	345337277	134501621	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	345337277	344641816	0	0
tb.dut.IntrErrO_A	0	0	345337277	344641816	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	345337277	344641816	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	345337277	344641816	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	345337277	344641816	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	345337277	344641816	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	345337277	344641816	0	0
tb.dut.MemRspPayLoad_A	0	0	345337277	4575241	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	345337277	344641816	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	345337277	344641816	0	0
tb.dut.MemTlDValidKnownO_A	0	0	345337277	344641816	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	345337277	344641816	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	345337277	344641816	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	345337277	344641816	0	0
tb.dut.RspPayLoad_A	0	0	345337277	39150452	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	345337277	344641816	0	0
tb.dut.TdoEnIsOne_A	0	0	345337277	344641816	0	0
tb.dut.TdoKnown_A	0	0	345337277	344641816	0	0
tb.dut.TlAReadyKnownO_A	0	0	345337277	344641816	0	0
tb.dut.TlDValidKnownO_A	0	0	345337277	344641816	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	348181253	3993	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	348181253	1819	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	348181253	2774	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	348181253	2310	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	348181253	2707	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	348181253	3428	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	348181253	2906	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	348181253	2262	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	348181253	2681	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	348181253	2728	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	348181253	3219	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	348181253	2959	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	348181253	2811	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	348181253	2192	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	348181253	2856	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	348181253	2759	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	348181253	2830	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	348181253	2773	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	348181253	2748	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	348181253	1885	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	348181253	2287	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	348181253	2308	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	348181253	2328	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	348181253	2168	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	348181253	2536	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	348181253	2027	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	348181253	1830	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	348181253	2320	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	348181253	3303	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	348181253	3164	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	348181253	3103	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	348181253	3429	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	348181253	3428	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	348181253	3553	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	348181253	3431	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	348181253	3546	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	348181253	3249	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	348181253	3215	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	348181253	1890	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	348181253	2235	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	348181253	2415	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	348181253	2844	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	348181253	2666	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	348181253	2343	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	348181253	2847	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	348181253	2877	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	348181253	2885	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	348181253	2748	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	348181253	2797	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	348181253	2879	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	348181253	2292	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	348181253	3458	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	348181253	2275	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	348181253	2925	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	348181253	2790	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	348181253	2711	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	348181253	2885	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	348181253	1896	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	348181253	2475	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	348181253	2297	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	348181253	3375	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	348181253	2431	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	348181253	2002	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	348181253	2003	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	348181253	2813	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	348181253	2781	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	348181253	2966	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	348181253	2438	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	348181253	2826	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	348181253	3356	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	348181253	2786	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	348181253	3339	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	348181253	2964	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	348181253	2799	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	348181253	2843	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	348181253	2775	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	348181253	3401	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	348181253	1197	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	348181253	2718	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	348181253	2236	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	348181253	2397	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	348181253	2422	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	348181253	2695	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	348181253	2896	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	348181253	2302	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	348181253	2398	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	348181253	2347	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	348181222	30994062	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	348181222	347400734	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	348181222	347400734	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	348181222	40008335	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	348181222	347400734	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	348181222	347400734	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1089	1089	0	0
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