Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1284 |
1 |
|
T9 |
26 |
|
T78 |
1 |
|
T39 |
6 |
| others[1] |
1231 |
1 |
|
T3 |
1 |
|
T9 |
19 |
|
T78 |
1 |
| others[2] |
1223 |
1 |
|
T4 |
1 |
|
T9 |
20 |
|
T11 |
1 |
| others[3] |
2025 |
1 |
|
T9 |
27 |
|
T78 |
1 |
|
T39 |
3 |
| false |
591 |
1 |
|
T6 |
1 |
|
T9 |
8 |
|
T78 |
2 |
| true |
305 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
119 |
1 |
|
T28 |
6 |
|
T218 |
1 |
|
T126 |
1 |
| others[1] |
117 |
1 |
|
T28 |
2 |
|
T50 |
1 |
|
T346 |
1 |
| others[2] |
113 |
1 |
|
T346 |
1 |
|
T348 |
1 |
|
T131 |
4 |
| others[3] |
168 |
1 |
|
T28 |
5 |
|
T218 |
1 |
|
T233 |
1 |
| false |
56 |
1 |
|
T349 |
1 |
|
T238 |
2 |
|
T131 |
2 |
| true |
6086 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T13 |
1 |
|
T183 |
1 |
|
T14 |
1 |
| others[1] |
237 |
1 |
|
T2 |
1 |
|
T28 |
3 |
|
T131 |
9 |
| others[2] |
253 |
1 |
|
T28 |
1 |
|
T131 |
9 |
|
T347 |
1 |
| others[3] |
367 |
1 |
|
T28 |
3 |
|
T95 |
1 |
|
T218 |
1 |
| false |
118 |
1 |
|
T28 |
1 |
|
T346 |
1 |
|
T131 |
3 |
| true |
5468 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1051 |
1 |
|
T5 |
1 |
|
T9 |
7 |
|
T17 |
1 |
| others[1] |
1034 |
1 |
|
T3 |
1 |
|
T9 |
7 |
|
T71 |
1 |
| others[2] |
1004 |
1 |
|
T9 |
18 |
|
T78 |
2 |
|
T39 |
4 |
| others[3] |
1717 |
1 |
|
T6 |
1 |
|
T12 |
1 |
|
T9 |
18 |
| false |
558 |
1 |
|
T9 |
3 |
|
T39 |
1 |
|
T43 |
3 |
| true |
1295 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T9 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T183 |
1 |
|
T50 |
1 |
|
T238 |
1 |
| others[1] |
231 |
1 |
|
T28 |
2 |
|
T348 |
1 |
|
T349 |
1 |
| others[2] |
223 |
1 |
|
T59 |
1 |
|
T13 |
1 |
|
T49 |
1 |
| others[3] |
360 |
1 |
|
T4 |
1 |
|
T71 |
1 |
|
T28 |
3 |
| false |
127 |
1 |
|
T28 |
1 |
|
T131 |
1 |
|
T154 |
4 |
| true |
5492 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T17 |
1 |
|
T346 |
1 |
|
T18 |
1 |
| others[1] |
238 |
1 |
|
T28 |
1 |
|
T183 |
1 |
|
T18 |
1 |
| others[2] |
211 |
1 |
|
T28 |
2 |
|
T84 |
1 |
|
T49 |
1 |
| others[3] |
345 |
1 |
|
T28 |
1 |
|
T218 |
1 |
|
T233 |
1 |
| false |
114 |
1 |
|
T28 |
1 |
|
T18 |
1 |
|
T131 |
2 |
| true |
5544 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T9 |
19 |
|
T78 |
2 |
|
T39 |
4 |
| others[1] |
1203 |
1 |
|
T9 |
19 |
|
T39 |
2 |
|
T43 |
2 |
| others[2] |
1215 |
1 |
|
T9 |
23 |
|
T78 |
1 |
|
T39 |
3 |
| others[3] |
2022 |
1 |
|
T6 |
1 |
|
T9 |
30 |
|
T39 |
5 |
| false |
634 |
1 |
|
T9 |
9 |
|
T11 |
1 |
|
T78 |
2 |
| true |
333 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T9 |
18 |
| others[1] |
1196 |
1 |
|
T12 |
1 |
|
T9 |
18 |
|
T78 |
1 |
| others[2] |
1205 |
1 |
|
T9 |
22 |
|
T78 |
1 |
|
T39 |
4 |
| others[3] |
2074 |
1 |
|
T9 |
32 |
|
T11 |
1 |
|
T78 |
1 |
| false |
649 |
1 |
|
T9 |
10 |
|
T78 |
2 |
|
T39 |
2 |
| true |
305 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
88 |
1 |
|
T28 |
2 |
|
T218 |
1 |
|
T131 |
3 |
| others[1] |
110 |
1 |
|
T28 |
2 |
|
T348 |
1 |
|
T131 |
8 |
| others[2] |
119 |
1 |
|
T28 |
4 |
|
T13 |
1 |
|
T218 |
1 |
| others[3] |
164 |
1 |
|
T28 |
4 |
|
T233 |
1 |
|
T349 |
2 |
| false |
50 |
1 |
|
T28 |
1 |
|
T131 |
6 |
|
T347 |
1 |
| true |
6128 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T28 |
2 |
|
T218 |
1 |
|
T14 |
1 |
| others[1] |
226 |
1 |
|
T71 |
1 |
|
T33 |
1 |
|
T28 |
1 |
| others[2] |
241 |
1 |
|
T4 |
1 |
|
T28 |
1 |
|
T218 |
1 |
| others[3] |
363 |
1 |
|
T59 |
1 |
|
T28 |
1 |
|
T346 |
1 |
| false |
113 |
1 |
|
T2 |
1 |
|
T28 |
2 |
|
T18 |
2 |
| true |
5514 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1011 |
1 |
|
T9 |
9 |
|
T39 |
4 |
|
T43 |
2 |
| others[1] |
1058 |
1 |
|
T9 |
12 |
|
T39 |
2 |
|
T33 |
1 |
| others[2] |
1082 |
1 |
|
T6 |
1 |
|
T12 |
1 |
|
T9 |
13 |
| others[3] |
1682 |
1 |
|
T2 |
1 |
|
T9 |
15 |
|
T17 |
1 |
| false |
519 |
1 |
|
T9 |
2 |
|
T59 |
1 |
|
T78 |
3 |
| true |
1307 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T28 |
1 |
|
T95 |
1 |
|
T238 |
1 |
| others[1] |
244 |
1 |
|
T183 |
1 |
|
T14 |
1 |
|
T349 |
2 |
| others[2] |
231 |
1 |
|
T28 |
2 |
|
T13 |
1 |
|
T218 |
1 |
| others[3] |
365 |
1 |
|
T59 |
1 |
|
T33 |
1 |
|
T28 |
2 |
| false |
114 |
1 |
|
T348 |
1 |
|
T131 |
3 |
|
T347 |
1 |
| true |
5480 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T33 |
1 |
|
T28 |
3 |
|
T95 |
1 |
| others[1] |
256 |
1 |
|
T28 |
2 |
|
T346 |
1 |
|
T238 |
1 |
| others[2] |
202 |
1 |
|
T28 |
2 |
|
T84 |
1 |
|
T233 |
1 |
| others[3] |
376 |
1 |
|
T28 |
1 |
|
T183 |
1 |
|
T174 |
1 |
| false |
120 |
1 |
|
T13 |
1 |
|
T131 |
6 |
|
T241 |
1 |
| true |
5486 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1206 |
1 |
|
T9 |
17 |
|
T78 |
2 |
|
T39 |
4 |
| others[1] |
1211 |
1 |
|
T4 |
1 |
|
T9 |
19 |
|
T39 |
2 |
| others[2] |
1230 |
1 |
|
T6 |
1 |
|
T9 |
22 |
|
T11 |
1 |
| others[3] |
2055 |
1 |
|
T9 |
37 |
|
T78 |
2 |
|
T39 |
6 |
| false |
631 |
1 |
|
T9 |
5 |
|
T39 |
2 |
|
T43 |
1 |
| true |
326 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1182 |
1 |
|
T4 |
1 |
|
T9 |
17 |
|
T78 |
1 |
| others[1] |
1212 |
1 |
|
T9 |
22 |
|
T11 |
1 |
|
T39 |
2 |
| others[2] |
1259 |
1 |
|
T6 |
1 |
|
T9 |
15 |
|
T39 |
5 |
| others[3] |
2073 |
1 |
|
T9 |
37 |
|
T78 |
3 |
|
T39 |
3 |
| false |
633 |
1 |
|
T9 |
9 |
|
T78 |
1 |
|
T39 |
2 |
| true |
300 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T28 |
3 |
|
T131 |
3 |
|
T354 |
1 |
| others[1] |
106 |
1 |
|
T28 |
2 |
|
T218 |
1 |
|
T238 |
2 |
| others[2] |
111 |
1 |
|
T28 |
2 |
|
T131 |
3 |
|
T347 |
1 |
| others[3] |
188 |
1 |
|
T28 |
5 |
|
T218 |
1 |
|
T233 |
1 |
| false |
55 |
1 |
|
T28 |
1 |
|
T346 |
1 |
|
T131 |
6 |
| true |
6100 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T28 |
2 |
|
T49 |
1 |
|
T18 |
1 |
| others[1] |
242 |
1 |
|
T59 |
1 |
|
T28 |
1 |
|
T190 |
1 |
| others[2] |
241 |
1 |
|
T4 |
1 |
|
T28 |
1 |
|
T218 |
1 |
| others[3] |
371 |
1 |
|
T71 |
1 |
|
T28 |
1 |
|
T18 |
1 |
| false |
113 |
1 |
|
T28 |
1 |
|
T18 |
1 |
|
T349 |
2 |
| true |
5487 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1068 |
1 |
|
T12 |
1 |
|
T9 |
11 |
|
T71 |
1 |
| others[1] |
960 |
1 |
|
T6 |
1 |
|
T9 |
7 |
|
T78 |
2 |
| others[2] |
1051 |
1 |
|
T9 |
11 |
|
T39 |
4 |
|
T43 |
2 |
| others[3] |
1667 |
1 |
|
T9 |
12 |
|
T17 |
1 |
|
T78 |
1 |
| false |
580 |
1 |
|
T4 |
1 |
|
T9 |
4 |
|
T78 |
1 |
| true |
1333 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T12 |
1 |
|
T238 |
1 |
|
T147 |
1 |
| others[1] |
213 |
1 |
|
T233 |
1 |
|
T190 |
1 |
|
T131 |
4 |
| others[2] |
232 |
1 |
|
T17 |
1 |
|
T33 |
1 |
|
T28 |
1 |
| others[3] |
371 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T28 |
3 |
| false |
114 |
1 |
|
T28 |
2 |
|
T13 |
1 |
|
T84 |
1 |
| true |
5502 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T28 |
2 |
|
T218 |
2 |
|
T346 |
1 |
| others[1] |
234 |
1 |
|
T28 |
1 |
|
T49 |
1 |
|
T50 |
1 |
| others[2] |
207 |
1 |
|
T33 |
1 |
|
T28 |
2 |
|
T18 |
1 |
| others[3] |
359 |
1 |
|
T17 |
1 |
|
T28 |
3 |
|
T18 |
3 |
| false |
118 |
1 |
|
T95 |
1 |
|
T233 |
1 |
|
T126 |
1 |
| true |
5501 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1233 |
1 |
|
T9 |
21 |
|
T78 |
2 |
|
T39 |
5 |
| others[1] |
1221 |
1 |
|
T9 |
14 |
|
T78 |
1 |
|
T39 |
4 |
| others[2] |
1261 |
1 |
|
T9 |
17 |
|
T78 |
1 |
|
T39 |
2 |
| others[3] |
1967 |
1 |
|
T6 |
1 |
|
T9 |
38 |
|
T11 |
1 |
| false |
651 |
1 |
|
T9 |
10 |
|
T39 |
1 |
|
T27 |
4 |
| true |
326 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1211 |
1 |
|
T9 |
21 |
|
T17 |
1 |
|
T78 |
2 |
| others[1] |
1198 |
1 |
|
T6 |
1 |
|
T9 |
18 |
|
T11 |
1 |
| others[2] |
1218 |
1 |
|
T9 |
17 |
|
T78 |
1 |
|
T39 |
5 |
| others[3] |
2099 |
1 |
|
T9 |
39 |
|
T78 |
2 |
|
T39 |
6 |
| false |
630 |
1 |
|
T9 |
5 |
|
T39 |
1 |
|
T43 |
2 |
| true |
303 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T28 |
1 |
|
T218 |
1 |
|
T131 |
2 |
| others[1] |
92 |
1 |
|
T28 |
1 |
|
T238 |
1 |
|
T131 |
4 |
| others[2] |
106 |
1 |
|
T28 |
6 |
|
T218 |
1 |
|
T183 |
1 |
| others[3] |
168 |
1 |
|
T28 |
3 |
|
T13 |
1 |
|
T346 |
2 |
| false |
61 |
1 |
|
T28 |
2 |
|
T349 |
1 |
|
T131 |
3 |
| true |
6134 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T28 |
2 |
|
T183 |
1 |
|
T131 |
11 |
| others[1] |
231 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T18 |
1 |
| others[2] |
244 |
1 |
|
T28 |
2 |
|
T174 |
1 |
|
T131 |
10 |
| others[3] |
389 |
1 |
|
T71 |
1 |
|
T28 |
4 |
|
T95 |
1 |
| false |
108 |
1 |
|
T12 |
1 |
|
T131 |
8 |
|
T347 |
1 |
| true |
5476 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1042 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T5 |
1 |
| others[1] |
1041 |
1 |
|
T9 |
6 |
|
T78 |
1 |
|
T43 |
1 |
| others[2] |
954 |
1 |
|
T9 |
7 |
|
T78 |
1 |
|
T39 |
4 |
| others[3] |
1706 |
1 |
|
T9 |
19 |
|
T17 |
1 |
|
T39 |
7 |
| false |
552 |
1 |
|
T12 |
1 |
|
T9 |
5 |
|
T78 |
2 |
| true |
1364 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T9 |
60 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T28 |
3 |
|
T13 |
1 |
|
T346 |
1 |
| others[1] |
221 |
1 |
|
T71 |
1 |
|
T28 |
1 |
|
T218 |
1 |
| others[2] |
217 |
1 |
|
T28 |
1 |
|
T218 |
1 |
|
T346 |
1 |
| others[3] |
389 |
1 |
|
T2 |
1 |
|
T12 |
1 |
|
T59 |
1 |
| false |
128 |
1 |
|
T28 |
2 |
|
T147 |
1 |
|
T131 |
3 |
| true |
5494 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T33 |
1 |
|
T28 |
1 |
|
T131 |
14 |
| others[1] |
205 |
1 |
|
T18 |
2 |
|
T126 |
1 |
|
T131 |
6 |
| others[2] |
243 |
1 |
|
T18 |
2 |
|
T131 |
10 |
|
T154 |
8 |
| others[3] |
375 |
1 |
|
T28 |
2 |
|
T218 |
1 |
|
T183 |
1 |
| false |
122 |
1 |
|
T84 |
1 |
|
T131 |
3 |
|
T154 |
4 |
| true |
5508 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T9 |
21 |
|
T78 |
2 |
|
T39 |
1 |
| others[1] |
1230 |
1 |
|
T9 |
23 |
|
T39 |
1 |
|
T43 |
5 |
| others[2] |
1239 |
1 |
|
T9 |
22 |
|
T11 |
1 |
|
T78 |
3 |
| others[3] |
1982 |
1 |
|
T9 |
29 |
|
T39 |
4 |
|
T43 |
1 |
| false |
619 |
1 |
|
T6 |
1 |
|
T9 |
5 |
|
T39 |
3 |
| true |
329 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T41 |
1 |
|
T355 |
1 |
|
T356 |
1 |
| others[1] |
5 |
1 |
|
T5 |
1 |
|
T60 |
1 |
|
T357 |
1 |
| others[2] |
8 |
1 |
|
T31 |
1 |
|
T121 |
1 |
|
T358 |
1 |
| others[3] |
12 |
1 |
|
T104 |
1 |
|
T106 |
1 |
|
T359 |
1 |
| false |
1 |
1 |
|
T360 |
1 |
|
- |
- |
|
- |
- |
| true |
50 |
1 |
|
T22 |
1 |
|
T60 |
1 |
|
T119 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T361 |
1 |
|
T362 |
1 |
|
T363 |
1 |
| others[1] |
1 |
1 |
|
T364 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
1 |
1 |
|
T365 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
6 |
1 |
|
T80 |
1 |
|
T82 |
1 |
|
T141 |
1 |
| false |
6 |
1 |
|
T366 |
1 |
|
T367 |
1 |
|
T368 |
1 |
| true |
30 |
1 |
|
T1 |
1 |
|
T79 |
1 |
|
T369 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T370 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
2 |
1 |
|
T141 |
1 |
|
T371 |
1 |
|
- |
- |
| others[2] |
1 |
1 |
|
T372 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
3 |
1 |
|
T373 |
1 |
|
T367 |
1 |
|
T374 |
1 |
| false |
10 |
1 |
|
T361 |
1 |
|
T375 |
1 |
|
T376 |
1 |
| true |
30 |
1 |
|
T1 |
1 |
|
T79 |
1 |
|
T80 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |