Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10521 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
791 |
1 |
|
T16 |
1 |
|
T78 |
1 |
|
T39 |
4 |
| others[2] |
738 |
1 |
|
T6 |
1 |
|
T78 |
1 |
|
T39 |
1 |
| others[3] |
1283 |
1 |
|
T78 |
3 |
|
T39 |
7 |
|
T43 |
5 |
| false |
394 |
1 |
|
T39 |
1 |
|
T43 |
2 |
|
T27 |
2 |
| true |
417 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2510 |
1 |
|
T25 |
51 |
|
T9 |
20 |
|
T39 |
4 |
| others[1] |
2436 |
1 |
|
T25 |
47 |
|
T9 |
17 |
|
T10 |
2 |
| others[2] |
2474 |
1 |
|
T25 |
49 |
|
T9 |
15 |
|
T78 |
2 |
| others[3] |
4059 |
1 |
|
T25 |
68 |
|
T9 |
40 |
|
T78 |
2 |
| false |
1215 |
1 |
|
T6 |
1 |
|
T25 |
32 |
|
T9 |
8 |
| true |
1450 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9952 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T71 |
1 |
| others[1] |
240 |
1 |
|
T17 |
1 |
|
T28 |
1 |
|
T13 |
1 |
| others[2] |
278 |
1 |
|
T8 |
1 |
|
T350 |
1 |
|
T232 |
1 |
| others[3] |
443 |
1 |
|
T4 |
1 |
|
T28 |
5 |
|
T174 |
1 |
| false |
140 |
1 |
|
T28 |
2 |
|
T232 |
1 |
|
T346 |
1 |
| true |
3091 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10197 |
1 |
|
T6 |
1 |
|
T25 |
247 |
|
T9 |
100 |
| others[1] |
433 |
1 |
|
T43 |
2 |
|
T27 |
1 |
|
T28 |
1 |
| others[2] |
427 |
1 |
|
T78 |
1 |
|
T39 |
2 |
|
T33 |
1 |
| others[3] |
783 |
1 |
|
T2 |
1 |
|
T71 |
1 |
|
T78 |
1 |
| false |
219 |
1 |
|
T39 |
1 |
|
T28 |
3 |
|
T177 |
3 |
| true |
2085 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9989 |
1 |
|
T4 |
1 |
|
T25 |
247 |
|
T9 |
100 |
| others[1] |
230 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T13 |
1 |
| others[2] |
251 |
1 |
|
T59 |
1 |
|
T17 |
1 |
|
T28 |
1 |
| others[3] |
415 |
1 |
|
T6 |
1 |
|
T33 |
1 |
|
T28 |
1 |
| false |
123 |
1 |
|
T147 |
1 |
|
T131 |
2 |
|
T154 |
3 |
| true |
3136 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9949 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
239 |
1 |
|
T7 |
1 |
|
T28 |
3 |
|
T348 |
1 |
| others[2] |
234 |
1 |
|
T6 |
1 |
|
T28 |
1 |
|
T218 |
1 |
| others[3] |
444 |
1 |
|
T28 |
3 |
|
T350 |
1 |
|
T183 |
1 |
| false |
141 |
1 |
|
T28 |
1 |
|
T95 |
1 |
|
T131 |
5 |
| true |
3137 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10530 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
745 |
1 |
|
T78 |
1 |
|
T39 |
1 |
|
T7 |
1 |
| others[2] |
773 |
1 |
|
T6 |
1 |
|
T39 |
5 |
|
T43 |
4 |
| others[3] |
1295 |
1 |
|
T78 |
4 |
|
T39 |
5 |
|
T43 |
3 |
| false |
411 |
1 |
|
T39 |
3 |
|
T43 |
2 |
|
T27 |
2 |
| true |
390 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10499 |
1 |
|
T6 |
1 |
|
T25 |
247 |
|
T9 |
100 |
| others[1] |
771 |
1 |
|
T78 |
2 |
|
T39 |
4 |
|
T43 |
6 |
| others[2] |
721 |
1 |
|
T39 |
1 |
|
T43 |
1 |
|
T27 |
3 |
| others[3] |
1343 |
1 |
|
T16 |
1 |
|
T78 |
3 |
|
T39 |
4 |
| false |
358 |
1 |
|
T39 |
1 |
|
T33 |
1 |
|
T177 |
4 |
| true |
424 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2389 |
1 |
|
T25 |
44 |
|
T9 |
20 |
|
T78 |
1 |
| others[1] |
2411 |
1 |
|
T25 |
41 |
|
T9 |
18 |
|
T39 |
1 |
| others[2] |
2506 |
1 |
|
T25 |
54 |
|
T9 |
20 |
|
T10 |
1 |
| others[3] |
4089 |
1 |
|
T6 |
1 |
|
T25 |
87 |
|
T9 |
35 |
| false |
1251 |
1 |
|
T25 |
21 |
|
T9 |
7 |
|
T78 |
2 |
| true |
1470 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9957 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
266 |
1 |
|
T28 |
2 |
|
T232 |
2 |
|
T233 |
1 |
| others[2] |
237 |
1 |
|
T2 |
1 |
|
T232 |
1 |
|
T18 |
1 |
| others[3] |
463 |
1 |
|
T6 |
1 |
|
T18 |
1 |
|
T147 |
1 |
| false |
137 |
1 |
|
T28 |
2 |
|
T8 |
1 |
|
T232 |
1 |
| true |
3056 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10166 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
475 |
1 |
|
T17 |
1 |
|
T78 |
1 |
|
T39 |
2 |
| others[2] |
428 |
1 |
|
T39 |
1 |
|
T43 |
2 |
|
T27 |
2 |
| others[3] |
728 |
1 |
|
T2 |
1 |
|
T78 |
1 |
|
T39 |
3 |
| false |
238 |
1 |
|
T5 |
1 |
|
T59 |
1 |
|
T39 |
2 |
| true |
2081 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9962 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T25 |
247 |
| others[1] |
244 |
1 |
|
T7 |
1 |
|
T28 |
1 |
|
T95 |
1 |
| others[2] |
262 |
1 |
|
T71 |
1 |
|
T28 |
3 |
|
T233 |
1 |
| others[3] |
433 |
1 |
|
T33 |
1 |
|
T28 |
3 |
|
T218 |
1 |
| false |
124 |
1 |
|
T28 |
1 |
|
T131 |
6 |
|
T142 |
1 |
| true |
3091 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9932 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
269 |
1 |
|
T7 |
1 |
|
T218 |
1 |
|
T50 |
1 |
| others[2] |
243 |
1 |
|
T28 |
4 |
|
T218 |
1 |
|
T49 |
1 |
| others[3] |
398 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T28 |
1 |
| false |
134 |
1 |
|
T95 |
1 |
|
T131 |
6 |
|
T154 |
5 |
| true |
3140 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10511 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
734 |
1 |
|
T39 |
4 |
|
T7 |
1 |
|
T43 |
5 |
| others[2] |
751 |
1 |
|
T4 |
1 |
|
T39 |
2 |
|
T43 |
2 |
| others[3] |
1301 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
| false |
409 |
1 |
|
T78 |
2 |
|
T39 |
3 |
|
T27 |
1 |
| true |
410 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10455 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
740 |
1 |
|
T6 |
1 |
|
T39 |
5 |
|
T43 |
3 |
| others[2] |
800 |
1 |
|
T78 |
1 |
|
T39 |
4 |
|
T43 |
2 |
| others[3] |
1314 |
1 |
|
T16 |
1 |
|
T78 |
4 |
|
T39 |
5 |
| false |
392 |
1 |
|
T43 |
1 |
|
T27 |
3 |
|
T177 |
8 |
| true |
415 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2407 |
1 |
|
T25 |
51 |
|
T9 |
16 |
|
T78 |
1 |
| others[1] |
2447 |
1 |
|
T25 |
50 |
|
T9 |
25 |
|
T10 |
1 |
| others[2] |
2469 |
1 |
|
T25 |
41 |
|
T9 |
18 |
|
T10 |
1 |
| others[3] |
4063 |
1 |
|
T6 |
1 |
|
T25 |
74 |
|
T9 |
32 |
| false |
1292 |
1 |
|
T25 |
31 |
|
T9 |
9 |
|
T78 |
1 |
| true |
1438 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9975 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
271 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T28 |
1 |
| others[2] |
247 |
1 |
|
T28 |
1 |
|
T232 |
1 |
|
T76 |
1 |
| others[3] |
414 |
1 |
|
T28 |
2 |
|
T232 |
5 |
|
T18 |
1 |
| false |
125 |
1 |
|
T71 |
1 |
|
T28 |
2 |
|
T14 |
1 |
| true |
3084 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10156 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T25 |
247 |
| others[1] |
413 |
1 |
|
T59 |
1 |
|
T78 |
2 |
|
T39 |
1 |
| others[2] |
457 |
1 |
|
T71 |
1 |
|
T43 |
1 |
|
T28 |
2 |
| others[3] |
784 |
1 |
|
T5 |
1 |
|
T12 |
1 |
|
T39 |
5 |
| false |
245 |
1 |
|
T43 |
2 |
|
T27 |
2 |
|
T28 |
3 |
| true |
2061 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9952 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
273 |
1 |
|
T2 |
1 |
|
T28 |
3 |
|
T349 |
1 |
| others[2] |
270 |
1 |
|
T28 |
1 |
|
T13 |
1 |
|
T74 |
1 |
| others[3] |
433 |
1 |
|
T4 |
1 |
|
T12 |
1 |
|
T17 |
1 |
| false |
124 |
1 |
|
T28 |
1 |
|
T218 |
1 |
|
T131 |
2 |
| true |
3064 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9972 |
1 |
|
T6 |
1 |
|
T25 |
247 |
|
T9 |
100 |
| others[1] |
238 |
1 |
|
T28 |
2 |
|
T50 |
1 |
|
T346 |
1 |
| others[2] |
263 |
1 |
|
T17 |
1 |
|
T28 |
2 |
|
T49 |
1 |
| others[3] |
436 |
1 |
|
T28 |
1 |
|
T13 |
1 |
|
T18 |
1 |
| false |
103 |
1 |
|
T33 |
1 |
|
T183 |
1 |
|
T349 |
1 |
| true |
3104 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10484 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
818 |
1 |
|
T78 |
1 |
|
T39 |
2 |
|
T43 |
1 |
| others[2] |
770 |
1 |
|
T78 |
1 |
|
T39 |
2 |
|
T7 |
1 |
| others[3] |
1220 |
1 |
|
T12 |
1 |
|
T78 |
2 |
|
T39 |
3 |
| false |
424 |
1 |
|
T6 |
1 |
|
T78 |
1 |
|
T39 |
3 |
| true |
400 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10458 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
792 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T39 |
5 |
| others[2] |
759 |
1 |
|
T78 |
1 |
|
T39 |
4 |
|
T43 |
4 |
| others[3] |
1320 |
1 |
|
T78 |
2 |
|
T39 |
4 |
|
T43 |
3 |
| false |
368 |
1 |
|
T39 |
2 |
|
T7 |
1 |
|
T27 |
2 |
| true |
419 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2528 |
1 |
|
T25 |
54 |
|
T9 |
23 |
|
T39 |
3 |
| others[1] |
2426 |
1 |
|
T25 |
47 |
|
T9 |
21 |
|
T10 |
1 |
| others[2] |
2404 |
1 |
|
T6 |
1 |
|
T25 |
37 |
|
T9 |
15 |
| others[3] |
4017 |
1 |
|
T25 |
85 |
|
T9 |
29 |
|
T11 |
1 |
| false |
1269 |
1 |
|
T25 |
24 |
|
T9 |
12 |
|
T39 |
2 |
| true |
1472 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9967 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
275 |
1 |
|
T6 |
1 |
|
T28 |
2 |
|
T13 |
1 |
| others[2] |
266 |
1 |
|
T28 |
1 |
|
T232 |
1 |
|
T346 |
1 |
| others[3] |
422 |
1 |
|
T4 |
1 |
|
T28 |
2 |
|
T218 |
1 |
| false |
111 |
1 |
|
T59 |
1 |
|
T28 |
1 |
|
T50 |
1 |
| true |
3075 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10159 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
438 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T78 |
1 |
| others[2] |
431 |
1 |
|
T5 |
1 |
|
T71 |
1 |
|
T78 |
1 |
| others[3] |
751 |
1 |
|
T12 |
1 |
|
T16 |
1 |
|
T39 |
2 |
| false |
244 |
1 |
|
T78 |
1 |
|
T43 |
1 |
|
T28 |
2 |
| true |
2093 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9962 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T59 |
1 |
| others[1] |
264 |
1 |
|
T28 |
2 |
|
T95 |
1 |
|
T349 |
1 |
| others[2] |
236 |
1 |
|
T8 |
1 |
|
T183 |
1 |
|
T174 |
1 |
| others[3] |
407 |
1 |
|
T33 |
1 |
|
T28 |
3 |
|
T84 |
1 |
| false |
112 |
1 |
|
T4 |
1 |
|
T131 |
3 |
|
T154 |
7 |
| true |
3135 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9960 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
249 |
1 |
|
T28 |
2 |
|
T49 |
1 |
|
T131 |
8 |
| others[2] |
254 |
1 |
|
T7 |
1 |
|
T346 |
1 |
|
T18 |
1 |
| others[3] |
422 |
1 |
|
T6 |
1 |
|
T13 |
1 |
|
T50 |
1 |
| false |
103 |
1 |
|
T28 |
1 |
|
T131 |
3 |
|
T154 |
3 |
| true |
3128 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10505 |
1 |
|
T4 |
1 |
|
T25 |
247 |
|
T9 |
100 |
| others[1] |
767 |
1 |
|
T78 |
1 |
|
T39 |
3 |
|
T43 |
4 |
| others[2] |
771 |
1 |
|
T78 |
2 |
|
T43 |
2 |
|
T27 |
2 |
| others[3] |
1275 |
1 |
|
T6 |
1 |
|
T78 |
1 |
|
T39 |
5 |
| false |
408 |
1 |
|
T39 |
3 |
|
T43 |
1 |
|
T27 |
2 |
| true |
390 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10505 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
721 |
1 |
|
T6 |
1 |
|
T78 |
1 |
|
T39 |
2 |
| others[2] |
765 |
1 |
|
T39 |
3 |
|
T43 |
4 |
|
T27 |
3 |
| others[3] |
1269 |
1 |
|
T16 |
1 |
|
T78 |
1 |
|
T39 |
7 |
| false |
464 |
1 |
|
T78 |
2 |
|
T33 |
1 |
|
T7 |
1 |
| true |
392 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2450 |
1 |
|
T25 |
59 |
|
T9 |
22 |
|
T11 |
1 |
| others[1] |
2433 |
1 |
|
T25 |
61 |
|
T9 |
15 |
|
T10 |
1 |
| others[2] |
2479 |
1 |
|
T25 |
41 |
|
T9 |
19 |
|
T10 |
1 |
| others[3] |
4015 |
1 |
|
T6 |
1 |
|
T25 |
69 |
|
T9 |
33 |
| false |
1307 |
1 |
|
T25 |
17 |
|
T9 |
11 |
|
T39 |
2 |
| true |
1432 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9945 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
249 |
1 |
|
T6 |
1 |
|
T28 |
1 |
|
T13 |
1 |
| others[2] |
267 |
1 |
|
T28 |
2 |
|
T18 |
1 |
|
T15 |
1 |
| others[3] |
420 |
1 |
|
T4 |
1 |
|
T59 |
1 |
|
T28 |
2 |
| false |
126 |
1 |
|
T131 |
9 |
|
T347 |
1 |
|
T354 |
1 |
| true |
3109 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |