Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10171 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T71 |
1 |
| others[1] |
417 |
1 |
|
T78 |
1 |
|
T27 |
1 |
|
T28 |
2 |
| others[2] |
468 |
1 |
|
T12 |
1 |
|
T39 |
1 |
|
T7 |
1 |
| others[3] |
755 |
1 |
|
T59 |
1 |
|
T39 |
2 |
|
T43 |
2 |
| false |
223 |
1 |
|
T2 |
1 |
|
T39 |
2 |
|
T43 |
1 |
| true |
2082 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9953 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
277 |
1 |
|
T17 |
1 |
|
T28 |
1 |
|
T183 |
1 |
| others[2] |
230 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T33 |
1 |
| others[3] |
426 |
1 |
|
T6 |
1 |
|
T28 |
2 |
|
T13 |
1 |
| false |
119 |
1 |
|
T59 |
1 |
|
T28 |
1 |
|
T350 |
1 |
| true |
3111 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9946 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
240 |
1 |
|
T28 |
1 |
|
T95 |
1 |
|
T233 |
1 |
| others[2] |
263 |
1 |
|
T33 |
1 |
|
T28 |
2 |
|
T84 |
1 |
| others[3] |
375 |
1 |
|
T28 |
2 |
|
T13 |
1 |
|
T8 |
1 |
| false |
106 |
1 |
|
T18 |
1 |
|
T131 |
4 |
|
T81 |
1 |
| true |
3186 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10502 |
1 |
|
T6 |
1 |
|
T25 |
247 |
|
T9 |
100 |
| others[1] |
787 |
1 |
|
T39 |
4 |
|
T7 |
1 |
|
T43 |
1 |
| others[2] |
761 |
1 |
|
T78 |
1 |
|
T39 |
5 |
|
T43 |
1 |
| others[3] |
1287 |
1 |
|
T78 |
3 |
|
T39 |
2 |
|
T43 |
5 |
| false |
382 |
1 |
|
T16 |
1 |
|
T78 |
1 |
|
T27 |
2 |
| true |
397 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10474 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
782 |
1 |
|
T78 |
2 |
|
T39 |
4 |
|
T7 |
1 |
| others[2] |
724 |
1 |
|
T6 |
1 |
|
T39 |
2 |
|
T43 |
4 |
| others[3] |
1281 |
1 |
|
T16 |
1 |
|
T78 |
1 |
|
T39 |
4 |
| false |
454 |
1 |
|
T78 |
1 |
|
T39 |
1 |
|
T43 |
1 |
| true |
401 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2434 |
1 |
|
T25 |
54 |
|
T9 |
11 |
|
T10 |
1 |
| others[1] |
2508 |
1 |
|
T25 |
47 |
|
T9 |
21 |
|
T11 |
1 |
| others[2] |
2433 |
1 |
|
T25 |
49 |
|
T9 |
26 |
|
T78 |
2 |
| others[3] |
4036 |
1 |
|
T6 |
1 |
|
T25 |
73 |
|
T9 |
33 |
| false |
1270 |
1 |
|
T25 |
24 |
|
T9 |
9 |
|
T10 |
1 |
| true |
1435 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9961 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
259 |
1 |
|
T59 |
1 |
|
T28 |
1 |
|
T95 |
1 |
| others[2] |
284 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T74 |
1 |
| others[3] |
465 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T28 |
4 |
| false |
137 |
1 |
|
T4 |
1 |
|
T28 |
1 |
|
T18 |
1 |
| true |
3010 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10159 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
462 |
1 |
|
T39 |
2 |
|
T43 |
2 |
|
T27 |
3 |
| others[2] |
448 |
1 |
|
T78 |
1 |
|
T39 |
3 |
|
T33 |
1 |
| others[3] |
742 |
1 |
|
T59 |
1 |
|
T71 |
1 |
|
T43 |
1 |
| false |
201 |
1 |
|
T39 |
2 |
|
T43 |
3 |
|
T28 |
1 |
| true |
2104 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9953 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
246 |
1 |
|
T71 |
1 |
|
T28 |
2 |
|
T84 |
1 |
| others[2] |
256 |
1 |
|
T2 |
1 |
|
T28 |
2 |
|
T15 |
1 |
| others[3] |
425 |
1 |
|
T12 |
1 |
|
T7 |
1 |
|
T95 |
1 |
| false |
127 |
1 |
|
T4 |
1 |
|
T28 |
1 |
|
T126 |
1 |
| true |
3109 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9960 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
211 |
1 |
|
T28 |
1 |
|
T131 |
6 |
|
T241 |
1 |
| others[2] |
251 |
1 |
|
T131 |
9 |
|
T145 |
1 |
|
T154 |
10 |
| others[3] |
399 |
1 |
|
T28 |
4 |
|
T13 |
1 |
|
T218 |
1 |
| false |
119 |
1 |
|
T28 |
1 |
|
T84 |
1 |
|
T238 |
1 |
| true |
3176 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10504 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
794 |
1 |
|
T78 |
1 |
|
T39 |
2 |
|
T43 |
4 |
| others[2] |
764 |
1 |
|
T16 |
1 |
|
T78 |
2 |
|
T39 |
3 |
| others[3] |
1273 |
1 |
|
T78 |
1 |
|
T39 |
5 |
|
T43 |
3 |
| false |
373 |
1 |
|
T6 |
1 |
|
T39 |
1 |
|
T27 |
1 |
| true |
408 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10453 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
808 |
1 |
|
T78 |
2 |
|
T39 |
2 |
|
T43 |
5 |
| others[2] |
792 |
1 |
|
T39 |
4 |
|
T7 |
1 |
|
T43 |
2 |
| others[3] |
1262 |
1 |
|
T6 |
1 |
|
T78 |
2 |
|
T39 |
6 |
| false |
391 |
1 |
|
T39 |
2 |
|
T43 |
2 |
|
T27 |
1 |
| true |
410 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2432 |
1 |
|
T25 |
46 |
|
T9 |
28 |
|
T78 |
1 |
| others[1] |
2462 |
1 |
|
T25 |
52 |
|
T9 |
17 |
|
T78 |
1 |
| others[2] |
2472 |
1 |
|
T6 |
1 |
|
T25 |
48 |
|
T9 |
23 |
| others[3] |
4041 |
1 |
|
T25 |
67 |
|
T9 |
23 |
|
T10 |
1 |
| false |
1252 |
1 |
|
T25 |
34 |
|
T9 |
9 |
|
T11 |
1 |
| true |
1457 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9985 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
284 |
1 |
|
T28 |
4 |
|
T218 |
1 |
|
T74 |
1 |
| others[2] |
259 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T84 |
1 |
| others[3] |
423 |
1 |
|
T59 |
1 |
|
T28 |
2 |
|
T232 |
1 |
| false |
114 |
1 |
|
T28 |
1 |
|
T13 |
1 |
|
T238 |
1 |
| true |
3051 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10196 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
448 |
1 |
|
T16 |
1 |
|
T39 |
1 |
|
T33 |
1 |
| others[2] |
446 |
1 |
|
T78 |
1 |
|
T43 |
4 |
|
T27 |
4 |
| others[3] |
729 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
| false |
244 |
1 |
|
T43 |
2 |
|
T27 |
1 |
|
T28 |
2 |
| true |
2053 |
1 |
|
T6 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9937 |
1 |
|
T4 |
1 |
|
T25 |
247 |
|
T9 |
100 |
| others[1] |
249 |
1 |
|
T2 |
1 |
|
T12 |
1 |
|
T33 |
1 |
| others[2] |
279 |
1 |
|
T28 |
4 |
|
T131 |
11 |
|
T319 |
1 |
| others[3] |
406 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T28 |
1 |
| false |
141 |
1 |
|
T131 |
7 |
|
T154 |
6 |
|
T377 |
1 |
| true |
3104 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T59 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9962 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
265 |
1 |
|
T28 |
1 |
|
T18 |
1 |
|
T76 |
1 |
| others[2] |
263 |
1 |
|
T6 |
1 |
|
T33 |
1 |
|
T7 |
1 |
| others[3] |
399 |
1 |
|
T28 |
5 |
|
T18 |
1 |
|
T147 |
1 |
| false |
112 |
1 |
|
T28 |
1 |
|
T50 |
1 |
|
T18 |
2 |
| true |
3115 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10502 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
785 |
1 |
|
T16 |
1 |
|
T78 |
2 |
|
T39 |
3 |
| others[2] |
744 |
1 |
|
T6 |
1 |
|
T78 |
3 |
|
T39 |
5 |
| others[3] |
1259 |
1 |
|
T39 |
4 |
|
T43 |
6 |
|
T27 |
7 |
| false |
416 |
1 |
|
T39 |
1 |
|
T43 |
1 |
|
T27 |
2 |
| true |
410 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10498 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
775 |
1 |
|
T78 |
1 |
|
T39 |
5 |
|
T43 |
4 |
| others[2] |
779 |
1 |
|
T6 |
1 |
|
T78 |
3 |
|
T39 |
3 |
| others[3] |
1248 |
1 |
|
T78 |
1 |
|
T39 |
3 |
|
T43 |
3 |
| false |
413 |
1 |
|
T39 |
2 |
|
T7 |
1 |
|
T43 |
2 |
| true |
403 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2474 |
1 |
|
T25 |
58 |
|
T9 |
15 |
|
T39 |
3 |
| others[1] |
2483 |
1 |
|
T25 |
52 |
|
T9 |
19 |
|
T78 |
1 |
| others[2] |
2431 |
1 |
|
T6 |
1 |
|
T25 |
44 |
|
T9 |
32 |
| others[3] |
4069 |
1 |
|
T25 |
66 |
|
T9 |
22 |
|
T10 |
2 |
| false |
1248 |
1 |
|
T25 |
27 |
|
T9 |
12 |
|
T78 |
2 |
| true |
1411 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9968 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
289 |
1 |
|
T59 |
1 |
|
T17 |
1 |
|
T218 |
2 |
| others[2] |
261 |
1 |
|
T71 |
1 |
|
T28 |
1 |
|
T95 |
1 |
| others[3] |
418 |
1 |
|
T28 |
2 |
|
T13 |
1 |
|
T350 |
1 |
| false |
125 |
1 |
|
T6 |
1 |
|
T28 |
2 |
|
T232 |
1 |
| true |
3055 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10152 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T59 |
1 |
| others[1] |
438 |
1 |
|
T3 |
1 |
|
T71 |
1 |
|
T78 |
1 |
| others[2] |
449 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T39 |
2 |
| others[3] |
713 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T78 |
1 |
| false |
240 |
1 |
|
T39 |
1 |
|
T7 |
1 |
|
T43 |
2 |
| true |
2124 |
1 |
|
T4 |
1 |
|
T12 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9953 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
279 |
1 |
|
T218 |
1 |
|
T74 |
1 |
|
T346 |
2 |
| others[2] |
247 |
1 |
|
T28 |
2 |
|
T84 |
1 |
|
T49 |
1 |
| others[3] |
412 |
1 |
|
T6 |
1 |
|
T28 |
2 |
|
T13 |
1 |
| false |
147 |
1 |
|
T12 |
1 |
|
T28 |
1 |
|
T350 |
1 |
| true |
3078 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9945 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
245 |
1 |
|
T7 |
1 |
|
T28 |
1 |
|
T18 |
1 |
| others[2] |
261 |
1 |
|
T28 |
1 |
|
T218 |
1 |
|
T131 |
12 |
| others[3] |
401 |
1 |
|
T28 |
3 |
|
T13 |
1 |
|
T95 |
1 |
| false |
123 |
1 |
|
T50 |
1 |
|
T174 |
1 |
|
T238 |
1 |
| true |
3141 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10508 |
1 |
|
T25 |
247 |
|
T9 |
100 |
|
T10 |
2 |
| others[1] |
784 |
1 |
|
T12 |
1 |
|
T78 |
1 |
|
T39 |
3 |
| others[2] |
742 |
1 |
|
T39 |
1 |
|
T43 |
3 |
|
T27 |
3 |
| others[3] |
1299 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T78 |
3 |
| false |
389 |
1 |
|
T78 |
1 |
|
T39 |
4 |
|
T43 |
2 |
| true |
394 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |