Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	199696	1		T1	402		T2	56		T3	9
auto[FlashEraseBank]	223717	1		T2	26		T3	13		T4	649

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	234524	1		T1	12		T2	43		T3	9
auto[FlashOpProgram]	168758	1		T1	384		T3	13		T25	363
auto[FlashOpErase]	16131	1		T1	6		T2	39		T25	363
auto[FlashOpInvalid]	4000	1		T9	200		T83	200		T152	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	234524	1		T1	12		T2	43		T3	9
op[FlashOpProgram]	168758	1		T1	384		T3	13		T25	363
op[FlashOpErase]	16131	1		T1	6		T2	39		T25	363
read_erase_read	764	1		T1	2		T2	39		T59	8
read_prog_read	555	1		T12	1		T16	1		T17	4

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	297066	1		T2	1		T3	2		T4	939
auto[FlashPartInfo]	123783	1		T1	402		T2	81		T3	20
auto[FlashPartInfo1]	682	1		T11	64		T17	2		T95	2
auto[FlashPartInfo2]	1882	1		T12	2		T71	1		T11	128

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	168624	1		T2	1		T3	2		T4	939
auto[FlashPartData]	auto[FlashOpProgram]	120763	1		T9	99		T11	8192		T16	4
auto[FlashPartData]	auto[FlashOpErase]	3759	1		T9	99		T59	37		T71	11
auto[FlashPartData]	auto[FlashOpInvalid]	3920	1		T9	198		T83	194		T152	196
auto[FlashPartInfo]	auto[FlashOpRead]	64142	1		T1	12		T2	42		T3	7
auto[FlashPartInfo]	auto[FlashOpProgram]	47212	1		T1	384		T3	13		T25	363
auto[FlashPartInfo]	auto[FlashOpErase]	12359	1		T1	6		T2	39		T25	363
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T9	2		T83	6		T152	4
auto[FlashPartInfo1]	auto[FlashOpRead]	502	1		T11	32		T17	2		T95	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T11	32		T155	1		T158	32
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T132	1		T155	1		T136	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T155	2		T136	2		T137	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1256	1		T12	2		T71	1		T11	64
auto[FlashPartInfo2]	auto[FlashOpProgram]	617	1		T11	64		T17	5		T33	9
auto[FlashPartInfo2]	auto[FlashOpErase]	7	1		T132	1		T150	1		T135	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	2	1		T136	2		-	-		-	-