Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31019	1		T25	712		T9	400		T16	32
auto[1]	17	1		T280	4		T202	5		T320	4
auto[2]	25	1		T321	4		T322	1		T175	4
auto[3]	64	1		T12	2		T71	3		T95	4

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7780	1		T25	178		T9	100		T71	1
evic_idx[1]	7780	1		T25	178		T9	100		T71	1
evic_idx[2]	7784	1		T25	178		T12	1		T9	100
evic_idx[3]	7781	1		T25	178		T12	1		T9	100

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30272	1		T25	712		T9	400		T71	3
evic_op[2]	291	1		T12	2		T16	16		T39	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[2]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7558	1		T25	178		T9	100		T16	4
evic_idx[0]	evic_op[1]	auto[1]	1	1		T280	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	8	1		T71	1		T323	2		T324	2
evic_idx[0]	evic_op[2]	auto[0]	61	1		T16	4		T39	1		T232	4
evic_idx[0]	evic_op[2]	auto[1]	3	1		T202	1		T320	1		T325	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T321	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	7	1		T95	1		T48	1		T153	1
evic_idx[1]	evic_op[1]	auto[0]	7560	1		T25	178		T9	100		T16	4
evic_idx[1]	evic_op[1]	auto[1]	1	1		T280	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	8	1		T71	1		T323	2		T324	2
evic_idx[1]	evic_op[2]	auto[0]	59	1		T16	4		T232	4		T131	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T202	1		T320	2		T325	1
evic_idx[1]	evic_op[2]	auto[2]	1	1		T321	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	6	1		T95	1		T90	1		T75	1
evic_idx[2]	evic_op[1]	auto[0]	7560	1		T25	178		T9	100		T16	4
evic_idx[2]	evic_op[1]	auto[1]	1	1		T280	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	7	1		T323	3		T324	1		T326	3
evic_idx[2]	evic_op[2]	auto[0]	61	1		T16	4		T232	4		T207	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T202	2		T325	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	1	1		T321	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	10	1		T12	1		T95	1		T174	1
evic_idx[3]	evic_op[1]	auto[0]	7559	1		T25	178		T9	100		T16	4
evic_idx[3]	evic_op[1]	auto[1]	1	1		T280	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	8	1		T71	1		T323	3		T327	1
evic_idx[3]	evic_op[2]	auto[0]	59	1		T16	4		T43	1		T232	4
evic_idx[3]	evic_op[2]	auto[1]	3	1		T202	1		T320	1		T325	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T321	1		T322	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	10	1		T12	1		T95	1		T74	1